Patent application number | Description | Published |
20090085122 | POLY PROFILE ENGINEERING TO MODULATE SPACER INDUCED STRESS FOR DEVICE ENHANCEMENT - The present invention provides a method of inducing stress in a semiconductor device substrate by applying an ion implantation to a gate region before a source/drain annealing process. The source/drain region may then be annealed along with the gate which will cause the gate to expand in certain areas due to said ion implantation. As a result, stress caused by said expansion of the gate is transferred to the channel region in the semiconductor substrate. | 04-02-2009 |
20090315115 | Implantation for shallow trench isolation (STI) formation and for stress for transistor performance enhancement - A method (and semiconductor device) of fabricating a semiconductor device provides a shallow trench isolation (STI) structure or region by implanting ions in the STI region. After implantation, the region (of substrate material and ions of a different element) is thermally annealed producing a dielectric material operable for isolating two adjacent field-effect transistors (FET). This eliminates the conventional steps of removing substrate material to form the trench and refilling the trench with dielectric material. Implantation of nitrogen ions into an STI region adjacent a p-type FET applies a compressive stress to the transistor channel region to enhance transistor performance. Implantation of oxygen ions into an STI region adjacent an n-type FET applies a tensile stress to the transistor channel region to enhance transistor performance. | 12-24-2009 |
20100001370 | INTEGRATED CIRCUIT SYSTEM EMPLOYING ALTERNATING CONDUCTIVE LAYERS - An integrated circuit system that includes: providing a substrate including front-end-of-line circuitry; forming a first conductive level including a first conductive trace over the substrate; forming a second conductive level spaced apart from the first conductive level and including a second conductive trace; and connecting the first conductive level to a third conductive level with a viabar that passes through the second conductive level without contacting the second conductive trace. | 01-07-2010 |
20100044869 | RELIABLE INTERCONNECTS - A method for forming a semiconductor device is presented. The method includes providing a substrate prepared with a dielectric layer formed thereon. The dielectric layer having a conductive line disposed in an upper portion of the dielectric layer. The substrate is processed to produce a top surface of the dielectric layer that is not coplanar with a top surface of the conductive line to form a stepped topography. | 02-25-2010 |
20100314763 | INTEGRATED CIRCUIT SYSTEM EMPLOYING LOW-K DIELECTRICS AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit system includes: fabricating a substrate having an integrated circuit; applying a low-K dielectric layer over the integrated circuit; forming a via and a trench, in the low-K dielectric layer, over the integrated circuit; forming a structure surface by a chemical-mechanical planarization (CMP) process; and applying a direct implant to the structure surface for forming an implant layer and a metal passivation layer including repairing damage, to the low-K dielectric layer, caused by the CMP process. | 12-16-2010 |
20100314774 | RELIABLE INTERCONNECTS - A method for forming a semiconductor device is presented. The method includes providing a substrate prepared with a dielectric layer formed thereon. The dielectric layer having a conductive line disposed in an upper portion of the dielectric layer. The substrate is processed to produce a top surface of the dielectric layer that is not coplanar with a top surface of the conductive line to form a stepped topography. | 12-16-2010 |
20110266628 | POLY PROFILE ENGINEERING TO MODULATE SPACER INDUCED STRESS FOR DEVICE ENHANCEMENT - The present invention provides a method of inducing stress in a semiconductor device substrate by applying an ion implantation to a gate region before a source/drain annealing process. The source/drain region may then be annealed along with the gate which will cause the gate to expand in certain areas due to said ion implantation. As a result, stress caused by said expansion of the gate is transferred to the channel region in the semiconductor substrate. | 11-03-2011 |
20120168915 | RELIABLE INTERCONNECT INTEGRATION SCHEME - Embodiments relate to a method for forming reliable interconnects by preparing a substrate with a dielectric layer, processing the dielectric layer to serve as an IMD layer, wherein the IMD layer comprises a hybrid IMD layer comprising a plurality of dielectric materials with different k values. | 07-05-2012 |
20130105968 | TSV Backside Processing Using Copper Damascene Interconnect Technology | 05-02-2013 |
20130187280 | Crack-Arresting Structure for Through-Silicon Vias - The subject matter disclosed herein relates to structures formed on semiconductor chips that are used for at least partially addressing the thermally induced stresses and metallization system cracking problems in a semiconductor chip that may be caused by the presence of through-silicon vias (TSV's), and which may be due primarily to the significant differences in thermal expansion between the materials of the TSV's and the semiconductor-based materials that generally make up the remainder of the semiconductor chip. One device disclosed herein includes a substrate and a crack-arresting structure positioned above the substrate, the crack-arresting structure comprising a plurality of crack-arresting elements and having a perimeter when viewed from above. The device also includes a conductive structure positioned at least partially within the perimeter of the crack-arresting structure, and a conductive element extending through an opening in the crack-arresting structure, wherein the conductive element is conductively coupled to the conductive structure. | 07-25-2013 |
20130256834 | BACK-SIDE MOM/MIM DEVICES - Back-side MOM/MIM structures are integrated on a device with front-side circuitry. Embodiments include forming a substrate having a front side and a back side that is opposite the front side, the substrate including circuitry on the front side of the substrate; and forming a metal-oxide-metal (MOM) capacitor, a metal-insulator-metal (MIM) capacitor, or a combination thereof on the back side of the substrate. Other embodiments include forming a through-silicon via (TSV), in the substrate, connecting the MOM capacitor, the MIM capacitor, or a combination thereof to the circuitry on the front side of the substrate. | 10-03-2013 |
20130277810 | METHOD FOR FORMING HEAT SINK WITH THROUGH SILICON VIAS - Semiconductor devices are formed with through silicon vias extending into the semiconductor substrate from a backside surface for improved heat dissipation. Embodiments include forming a cavity in a backside surface of a substrate, the substrate including a gate stack on a frontside surface, and filling the cavity with a thermally conductive material. | 10-24-2013 |
20140035155 | DEVICE WITH INTEGRATED POWER SUPPLY - Semiconductor devices and methods for forming a semiconductor device are disclosed. The semiconductor device includes a die. The die includes a die substrate having first and second major surfaces. The semiconductor device includes a power module disposed below the second major surface of the die substrate. The power module is electrically coupled to the die through through silicon via (TSV) contacts. | 02-06-2014 |
20140191407 | DIELECTRIC POSTS IN METAL LAYERS - A semiconductor device is disclosed. The semiconductor device includes a substrate comprises a plurality of metal layers. The semiconductor device also includes dielectric posts disposed in the metal layers. The density of the dielectric posts in the metal layers is equal to about 15-25%. | 07-10-2014 |
20140264235 | NON-VOLATILE MEMORY DEVICE WITH TSI/TSV APPLICATION - Memory devices and methods for forming the device are disclosed. The device includes a substrate having an array surface and a non-array surface and a memory array having a plurality of memory cells interconnected by first conductors in a first direction and second conductors in a second direction. The memory array is disposed on the array surface of the substrate. The device further includes through silicon via (TSV) contacts disposed in the substrate. The TSV contacts extend from the array surface to the non-array surface, enabling electrical connections to the array from the non-array surface. | 09-18-2014 |
20140264733 | DEVICE WITH INTEGRATED PASSIVE COMPONENT - Semiconductor devices and methods for forming a semiconductor device are presented. The semiconductor device includes a die which includes a die substrate having first and second major surfaces. The semiconductor device includes a passive component disposed below the second major surface of the die substrate. The passive component is electrically coupled to the die through through silicon via (TSV) contacts. | 09-18-2014 |
20150028407 | 3D HIGH VOLTAGE CHARGE PUMP - A capacitor and method of forming a capacitor are presented. The capacitor includes a substrate having a capacitor region in which the capacitor is disposed. The capacitor includes first, second and third sub-capacitors (C1, C2 and C3). The C1 comprises a metal oxide semiconductor (MOS) capacitor which includes a gate on the substrate. The gate includes a gate electrode over a gate dielectric. A first C1 plate is served by the gate electrode, a second C1 plate is served by the substrate of the capacitor region and a C1 capacitor dielectric is served by the gate dielectric. The C2 includes a back-end-of-line (BEOL) vertical capacitor disposed in ILD layers with metal levels and via levels. A plurality of metal lines are disposed in the metal levels. The metal lines of a metal level are grouped in alternating first and second groups, the first group serves as first C2 plates and second group serves as second. C2 plates and the dielectric layers between the first and second groups serve as C2 capacitor dielectrics. The C3 includes a first C3 plate served by the gate electrode, a second C3 plate served by second group lines in the first metal level of the ILD layers, and a C3 capacitor dielectric is served by the first via level dielectric below M1 and above the gate electrode. A first capacitor terminal is coupled to first capacitor plates of C1, C2 and C3 and a second capacitor terminal is coupled to second capacitor plates of C1, C2 and C3. | 01-29-2015 |
20150061156 | PAD SOLUTIONS FOR RELIABLE BONDS - A bonding pad and a method of manufacturing a bonding pad are presented. The method includes providing a substrate prepared with circuits component and an interlevel dielectric (ILD) layer with interconnects. A final passivation level is formed on the substrate surface and includes a pad opening. A wire bond in contact with the pad interconnect is formed in the pad opening. The pad interconnect is suitable for, for example, copper wire bond and can avoid the formation of intermetallic compound during wire bonding. This Abstract is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims. | 03-05-2015 |
20150069561 | LOGIC COMPATIBLE MEMORY - A device and a method of forming a device are presented. A substrate is provided. Front end of line processing is performed to form circuit component on the substrate and back end of line processing is performed to include the uppermost inter level dielectric (ILD) layer. The uppermost ILD layer includes first and second interconnects. A pad level is formed over the uppermost ILD layer. A storage unit of a memory cell is provided in the pad level. The storage unit is coupled to the first interconnect of the uppermost ILD layer. A cell interconnect and a pad interconnect are formed in the pad level. The cell interconnect is formed on top of and coupled to the storage unit and the pad interconnect is coupled to the second interconnect in the uppermost ILD layer. | 03-12-2015 |
20150076669 | RELIABLE CONTACTS - Semiconductor devices and methods for forming a semiconductor device are presented. The method includes providing a substrate having a device component with a contact region. A contact dielectric layer is formed on the substrate, covering the substrate and device component. The contact dielectric layer includes a lower contact dielectric layer, an intermediate contact dielectric etch stop layer formed on the lower contact dielectric layer, and an upper contact dielectric layer formed on the intermediate contact dielectric etch stop layer. A contact opening is formed through the contact dielectric layer. The contact opening has an upper contact sidewall profile in the upper contact dielectric layer and a lower tapered contact sidewall profile in the lower contact dielectric layer. The tapered sidewall profile prevents shorting with the device component. | 03-19-2015 |