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Ju-Hyung
Ju-Hyung Ahn, Kyungki-Do KR
| Patent application number | Description | Published |
|---|---|---|
| 20110200760 | METHOD FOR MANUFACTURING THE COLOR CONTROLLED SAPPIRE - Disclosed herein is a method of manufacturing a color-controlled sapphire, comprising: vaporizing a metal material, irradiating the vaporized metal material with electron beams or high-frequency waves to form the vaporized metal material into a plasma state, and then implanting the metal ions into a sapphire by extracting the metal ions from the plasma and accelerating the metal ions (step 1); and heat-treating the sapphire implanted with the metal plasma ions in an oxygen atmosphere or in air (step 2). According to the method of manufacturing a sapphire of the present invention, a sapphire, which can exhibit various colors, can be manufactured by implanting the ions, which can cause optical band gap changes into the sapphire, and a sapphire, which cannot be damaged by radiation and can exhibit colors uniformly, can be manufactured by conducting heat treatment under an oxygen atmosphere. Further, according to the present invention, a sapphire, which cannot be damaged by radiation and can be made to exhibit uniform colors, can be manufactured by performing the above processes repeatedly. | 08-18-2011 |
Ju-Hyung Hong, Gyeonnggi-Do KR
| Patent application number | Description | Published |
|---|---|---|
| 20090055713 | ECC CONTROL CIRCUITS, MULTI-CHANNEL MEMORY SYSTEMS INCLUDING THE SAME, AND RELATED METHODS OF OPERATION - An Error Correcting Code (ECC) control circuit in a memory controller includes an ECC controller configured to receive data from a memory device in response to a request from a host device. The ECC controller transmits the data to a direct memory access (DMA) buffer for transfer to the host device, and to an ECC block for error detection and correction of the data. The ECC controller is configured to interrupt transmission of the data to the DMA buffer and transmit error-corrected data output from the ECC block to the DMA buffer responsive to detection of an error in the data by the ECC block. Related systems and methods are also discussed. | 02-26-2009 |
Ju-Hyung Kim, Gyeonggi-Do KR
| Patent application number | Description | Published |
|---|---|---|
| 20090121275 | Non-Volatile Memory Devices Including Blocking and Interface Patterns Between Charge Storage Patterns and Control Electrodes and Related Methods - A non-volatile memory device may include a semiconductor substrate and an isolation layer on the semiconductor substrate wherein the isolation layer defines an active region of the semiconductor substrate. A tunnel insulation layer may be provided on the active region of the semiconductor substrate, and a charge storage pattern may be provided on the tunnel insulation layer. An interface layer pattern may be provided on the charge storage pattern, and a blocking insulation pattern may be provided on the interface layer pattern. Moreover, the block insulation pattern may include a high-k dielectric material, and the interface layer pattern and the blocking insulation pattern may include different materials. A control gate electrode may be provided on the blocking insulating layer so that the blocking insulation pattern is between the interface layer pattern and the control gate electrode. Related methods are also discussed. | 05-14-2009 |
Ju-Hyung Kim, Yongin-Si KR
| Patent application number | Description | Published |
|---|---|---|
| 20080237700 | Nonvolatile memory device having cell and peripheral regions and method of making the same - A nonvolatile memory device and method of making the same are provided. Memory cells may be provided in a cell area wherein each memory cell has an insulative structure including a tunnel insulating layer, a floating trap layer and a blocking layer, and a conductive structure including an energy barrier layer, a barrier metal layer and a low resistance gate electrode. A material having a lower resistivity may be used as the gate electrode so as to avoid problems associated with increased resistance and to allow the gate electrode to be made relatively thin. The memory device may further include transistors in the peripheral area, which may have a gate dielectric layer, a lower gate electrode of poly-silicon and an upper gate electrode made of metal silicide, allowing an improved interface with the lower gate electrode without diffusion or reaction while providing a lower resistance. | 10-02-2008 |
| 20090238004 | Method of operating sonos memory device - A silicon-oxide-nitride-oxide-silicon (SONOS) memory device includes a memory type transistor including a gate with a SONOS structure on a semiconductor substrate. The gate is formed by sequentially stacking a tunneling oxide layer, a memory node structure including a trap site having nano-sized trap elements in which charges passing through the tunneling oxide layer are trapped, and a gate electrode. The nano-sized trap elements may be a crystal layer composed of nanocrystals that are separated from one another to trap the charges. The memory node structure may include additional memory node layers which are isolated from the nano-sized trap elements. | 09-24-2009 |
| 20100301425 | SEMICONDUCTOR DEVICE HAVING A GATE CONTACT STRUCTURE CAPABLE OF REDUCING INTERFACIAL RESISTANCE - A semiconductor device has a gate contact structure, including a semiconductor substrate, a polycrystalline silicon layer used as a gate electrode of a transistor, a middle conductive layer, a top metal layer having an opening exposing the polycrystalline silicon layer, and a contact plug directly contacting the polycrystalline silicon layer through the opening. | 12-02-2010 |
| 20110037118 | Nonvolatile memory device having cell and peripheral regions and method of making the same - A nonvolatile memory device and method of making the same are provided. Memory cells may be provided in a cell area wherein each memory cell has an insulative structure including a tunnel insulating layer, a floating trap layer and a blocking layer, and a conductive structure including an energy barrier layer, a barrier metal layer and a low resistance gate electrode. A material having a lower resistivity may be used as the gate electrode so as to avoid problems associated with increased resistance and to allow the gate electrode to be made relatively thin. The memory device may further include transistors in the peripheral area, which may have a gate dielectric layer, a lower gate electrode of poly-silicon and an upper gate electrode made of metal silicide, allowing an improved interface with the lower gate electrode without diffusion or reaction while providing a lower resistance. | 02-17-2011 |
| 20110119564 | FLASH MEMORY DEVICE AND MEMORY SYSTEM COMPRISING SAME - A flash memory device provided here comprises a user data area storing user data; and a security data area storing security data. The security data area stores a security data pattern in which first groups of memory cells storing security data are arranged respectively between second groups of memory cells storing dummy data. | 05-19-2011 |
Ju-Hyung Kim, Seongnam-Si KR
| Patent application number | Description | Published |
|---|---|---|
| 20100133604 | Semiconductor Devices Having Gate Structures with Conductive Patterns of Different Widths and Methods of Fabricating Such Devices - A semiconductor device and a method of fabricating the same are provided. The semiconductor device includes a first dielectric pattern, a data storage pattern and a second dielectric pattern, which are sequentially stacked on a semiconductor substrate. A first conductive pattern is provided on the second dielectric pattern. A second conductive pattern having a greater width than the first conductive pattern is provided on the first conductive pattern. | 06-03-2010 |
Ju-Hyung Lee, San Jose, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20090145360 | METHOD AND APPARATUS FOR CLEANING A CVD CHAMBER - The present invention is a method and apparatus for cleaning a chemical vapor deposition (CVD) chamber using cleaning gas energized to a plasma in a gas mixing volume separated by an electrode from a reaction volume of the chamber. In one embodiment, a source of RF power is coupled to a lid of the chamber, while a switch is used to couple a showerhead to ground terminals or the source of RF power. | 06-11-2009 |
| 20100095891 | METHOD AND APPARATUS FOR CLEANING A CVD CHAMBER - The present invention is a method and apparatus for cleaning a chemical vapor deposition (CVD) chamber using cleaning gas energized to a plasma in a gas mixing volume separated by an electrode from a reaction volume of the chamber. In one embodiment, a source of RF power is coupled to a lid of the chamber, while a switch is used to couple a showerhead to ground terminals or the source of RF power. | 04-22-2010 |
Ju-Hyung Lee, Daejeon KR
| Patent application number | Description | Published |
|---|---|---|
| 20110163044 | CERAMIC STRUCTURE FOR WATER TREATMENT, WATER TREATMENT APPARATUS AND METHOD - A ceramic structure for water treatment, a water treatment apparatus and method are provided. Immersion efficiency of a photo catalyst and a specific surface area of the immersed photo catalyst can be improved using a ceramic medium including a ceramic paper prepared of a ceramic fiber. Accordingly, it is possible to provide the water treatment apparatus and method capable of increasing decomposition efficiency of contaminated materials due to irradiation of ultraviolet light, and so on, enabling continuous purification treatment, and remarkably reducing preparation, management and water treatment expenses. | 07-07-2011 |
Ju-Hyung Lee, Seoul KR
| Patent application number | Description | Published |
|---|---|---|
| 20100115899 | Ceramic Filter Comprising Clay and Process for Preparing Thereof - The present invention relates to a ceramic filter comprising clay and a process for preparing the same. More specifically, the present invention relates to the ceramic filter, including wave- shaped ceramic paper and plate-shaped paper, having improved efficiency and performance that may optimize the process of coating and calcining inorganic binder by forming an outer wall thereon, using clay, and thus increase insulation effect and mechanical strength represented by the clay layer, and the process for preparing thereof. | 05-13-2010 |
| 20100159358 | SEPARATOR FOR FUEL CELL AND FUEL CELL COMPRISING THE SAME - A separator for a fuel cell is provided. The separator comprises a flow path member and a base separator. The flow path member is made of a graphite foil and has a flow path through which fluids pass. The base separator has a seating recess formed on the surface thereof. The flow path member is mounted in the seating recess. The flow path is formed by pressing the graphite foil. The separator can be produced at reduced processing cost in a short processing time. | 06-24-2010 |
| 20110165049 | CATALYST FOR REMOVAL OF NTROGEN OXIDES FROM EXHAUST GAS, METHOD OF PREPARING THE SAME AND METHOD OF REMOVING NITROGEN OXIDES USING THE SAME FROM EXHAUST GAS - The present invention relates to a catalyst for removal of nitrogen oxides from exhaust gas, a method of preparing the same and a method of removing nitrogen oxide in an exhaust gas using the same, and more particularly, to a catalyst for removal of nitrogen oxides from exhaust gas in which a ceramic fiber carrier is hydrothermal-treated prior to washcoating to improve the hydrothermal stability of catalyst, a method of preparing the same and a method of removing nitrogen oxide in an exhaust gas using the same. | 07-07-2011 |
Ju-Hyung Lee, Gyeonggi-Do KR
| Patent application number | Description | Published |
|---|---|---|
| 20110305617 | CATALYST AND METHOD FOR REMOVING FORMALDEHYDE USING THE SAME - The present invention relates to a catalyst including a ceramic structure containing porous ceramic paper and a catalyst component supported on the ceramic structure, and to a method for removing formaldehyde using the catalyst. The present invention provides a catalyst in which a structure made of ceramic paper having excellent characteristics in terms of porosity, specific surface area, and the like is used as a support for the catalyst component to maximize an effective area for reacting the supported catalyst component with a substance to be treated, thereby improving catalyst performance. The present invention also provides a method of using the catalyst. | 12-15-2011 |
Ju-Hyung Park, Seoul KR
| Patent application number | Description | Published |
|---|---|---|
| 20080264844 | Plant for Wastewater Treatment - A plant for wastewater treatment is provided by an exemplary embodiment of the present invention. The plant for wastewater treatment includes a reactor into which wastewater and air flow into and depart from; multi-layer sludge separating portions, wherein pollutants in wastewater can be decomposed by increasing an amount of dissolved oxygen because upward moving time of intruded wastewater and air bubbles can be increased by including a reactor divided into upper and lower sides, and fluidity of wastewater may be improved by forming a residential space; and carriers located between the sludge separating portions and including a large amount of microbes, wherein wastewater treatment is performed by a biological reaction caused by contact between the carriers and wastewater. | 10-30-2008 |