Patent application number | Description | Published |
20120077339 | METHOD OF AND APPARATUS FOR ACTIVE ENERGY ASSIST BAKING - A method of and apparatus for forming interconnects on a substrate includes etching patterns in ultra-low k dielectric and removing moisture from the ultra-low k dielectric using active energy assist baking. During active energy assist baking, the ultra-low k dielectric is heated and exposed to light having only wavelengths greater than 400 nm for about 1 to about 20 minutes at a temperature of about 300 to about 400 degrees Celsius. The active energy assist baking is performed after wet-cleaning or after chemical mechanical polishing, or both. | 03-29-2012 |
20130137261 | METHOD OF MODIFYING A LOW K DIELECTRIC LAYER HAVING ETCHED FEATURES AND THE RESULTING PRODUCT - A dielectric layer having features etched thereon and a low dielectric constant, and that is carried by a semiconductor substrate. The etched dielectric layer is modified so its surface energy is reduced by at least one of: (a) applying thermal energy to the layer to cause the layer temperature to be between 100 C and 400 C; (b) irradiating the layer with electromagnetic energy; and/or (c) irradiating the layer with free ions. | 05-30-2013 |
20130256888 | INTERCONNECT STRUCTURE AND METHOD FOR FORMING THE SAME - A interconnect structure includes a first etch stop layer over a substrate, a dielectric layer over the first etch stop layer, a conductor in the dielectric layer, and a second etch stop layer over the dielectric layer. The dielectric layer contains carbon and has a top portion and a bottom potion. A difference of C content in the top portion and the bottom potion is less than 2 at %. An oxygen content in a surface of the conductor is less than about 1 at %. | 10-03-2013 |
20130256903 | INTERCONNECT STRUCTURE AND METHOD FOR FORMING THE SAME - A interconnect structure includes a conductive layer formed in a dielectric layer. An adhesion layer is formed between the dielectric layer and a substrate. The adhesion layer has a carbon content ratio greater than a carbon content ratio of the dielectric layer. | 10-03-2013 |
20130273732 | METHOD OF AND APPARATUS FOR ACTIVE ENERGY ASSIST BAKING - An Active Energy Assist (AEA) baking chamber includes an AEA light source assembly and a heater pedestal. The AEA baking chamber further includes a controller for controlling a power input to the AEA light source assembly and a power input to the heater pedestal. A method of forming interconnects on a substrate includes etching a substrate and wet cleaning the etched substrate. The method further includes active energy assist (AEA) baking the substrate after the wet-cleaning. The AEA baking includes placing the substrate on a heater pedestal in an AEA chamber, exposing the substrate to light having a wavelength equal to or greater than 400 nm, wherein said light is emitted by a light source and controlling the light source and the heater pedestal using a controller. | 10-17-2013 |
20140217589 | SUPPORT STRUCTURE FOR BARRIER LAYER OF SEMICONDUCTOR DEVICE - Among other things, one or more support structures and techniques for forming such support structures within semiconductor devices are provided. The support structure comprises an oxide infused silicon layer that is formed within a trench of a dielectric layer on a substrate of a semiconductor device. The oxide infused silicon layer results from a silicon layer that is exposed to oxide during an ultraviolet (UV) curing process. The oxide infused silicon layer is configured to support a barrier layer against a conductive structure formed on the barrier layer within the trench. In this way, the support structure provides pressure against the barrier layer so that the barrier layer substantially maintains contact with the conductive structure, to promote improved performance and reliability of the conductive structure. | 08-07-2014 |
20140264870 | METHOD OF BACK-END-OF-LINE (BEOL) FABRICATION, AND DEVICES FORMED BY THE METHOD - In a method for forming a semiconductor device, an interconnect structure over a semiconductor substrate is provided. The interconnect structure includes a first dielectric layer and a conductive pattern inside a trench in the first dielectric layer. An etch stop layer (ESL) is formed over the interconnect structure. An interface layer comprising elemental silicon is deposited over the ESL. A second dielectric layer is then formed over the interface layer. | 09-18-2014 |
20150048488 | Semiconductor Devices, Methods of Manufacture Thereof, and Inter-metal Dielectric (IMD) Structures - Semiconductor devices, methods of manufacture thereof, and IMD structures are disclosed. In some embodiments, a semiconductor device includes an adhesion layer disposed over a workpiece. The adhesion layer has a dielectric constant of about 4.0 or less and includes a substantially homogeneous material. An insulating material layer is disposed over the adhesion layer. The insulating material layer has a dielectric constant of about 2.6 or less. The adhesion layer and the insulating material layer comprise an IMD structure. | 02-19-2015 |
20150056555 | Photoresist and Method of Formation and Use - A system and method for depositing a photoresist and utilizing the photoresist are provided. In an embodiment a deposition chamber is utilized along with a first precursor material comprising carbon-carbon double bonds and a second precursor material comprising repeating units to deposit the photoresist onto a substrate. The first precursor material is turned into a plasma in a remote plasma chamber prior to being introduced into the deposition chamber. The resulting photoresist comprises a carbon backbone with carbon-carbon double bonds. | 02-26-2015 |
20150056802 | INTERCONNECT STRUCTURE AND METHOD FOR FORMING THE SAME - Embodiments of an interconnect structure and methods for forming an interconnect structure are provided. The method includes forming a low-k dielectric layer over a substrate, forming an opening in the low-k dielectric layer, forming a conductor in the opening, forming a capping layer over the conductor, and forming an etch stop layer over the capping layer and the low-k dielectric layer. The etch stop layer includes an N element with a content ratio not less than about 25 at %. | 02-26-2015 |