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Jou, TW
Chewn-Pu Jou, Chutung TW
| Patent application number | Description | Published |
|---|---|---|
| 20110186909 | ESD PROTECTION CIRCUIT FOR RFID TAG - An electrostatic discharge (ESD) protection circuit structure includes a dual directional silicon controlled rectifier (SCR) formed in a substrate. The SCR includes first and second P-wells laterally interposed by an N-well. A deep N-well is disposed underneath the P-wells and the N-well. First and second N-type regions are disposed in the first and second P-wells, respectively, and are coupled to a pair of pads. First and second P-type regions are disposed in the first and second P-wells, respectively, are coupled to the pads, and are disposed closer to the N-well than the first and second N-type regions, respectively. | 08-04-2011 |
| 20110233678 | JUNCTION VARACTOR FOR ESD PROTECTION OF RF CIRCUITS - An ESD protection device includes a first well of a first semiconductor type disposed in a substrate of a second semiconductor type forming a first diode. A second well of the second semiconductor type is formed in the substrate to form a second diode with the first well. A first plurality of doped regions of the first semiconductor type are formed in an upper surface of the first well. A second plurality of doped regions of the second semiconductor type are formed in the upper surface of the first well forming a third diode with the first well. A plurality of STI regions are formed in the upper surface of the first well. Each STI region is disposed between a doped region of the first and second semiconductor types. The third diode provides a current bypass when an ESD voltage spike is received at one of the first or second plurality of doped regions. | 09-29-2011 |
| 20110260819 | CONTINUOUSLY TUNABLE INDUCTOR WITH VARIABLE RESISTORS - An integrated tunable inductor includes a primary inductor having a plurality of inductor turns, at least one closed loop eddy current coil proximate the primary inductor, and at least one variable resistor integrated in series with the eddy current coil. | 10-27-2011 |
| 20110304372 | METHOD AND APPARATUS FOR AMPLIFYING A TIME DIFFERENCE - A time amplifier circuit has first and second inverters and first and second pull-down paths. Each inverter includes a first NMOS transistor and a first PMOS transistor. A source of the first NMOS transistor is coupled to a ground node directly or through a first additional NMOS transistor having a gate coupled to a respective input node. The first and second inverters are coupled to first and second input nodes and to first and second output nodes, respectively. The first pull-down path is from the first output node to the ground node and is enabled in response to the first input signal and the second output signal being high. The second pull-down path is from the second output node to ground and is enabled in response to the second input signal and the first output signal being high. | 12-15-2011 |
| 20120019968 | TRANSMISSION-LINE-BASED ESD PROTECTION - An ESD protection circuit includes a signal pad, a short circuited shunt stub on-chip with and coupled to the signal pad, an open circuited shunt stub on-chip and coupled to the signal pad. | 01-26-2012 |
| 20120032742 | CMOS MILLIMETER-WAVE VARIABLE-GAIN LOW-NOISE AMPLIFIER - A low-noise amplifier (LNA) includes a first cascode gain stage coupled to an input node for increasing an amplitude of an RF input signal. A first variable gain network is coupled to the first cascode gain stage and includes a first inductor for boosting a gain of the first cascode gain stage, a first capacitor coupled to the first inductor for blocking a direct current (DC) voltage, and a first switch coupled to the first inductor and to the first capacitor. The first switch is configured to selectively couple the first inductor to the first cascode gain stage in response to a first control signal. | 02-09-2012 |
| 20120032743 | LOW-NOISE AMPLIFIER WITH GAIN ENHANCEMENT - A low-noise amplifier (“LNA”) includes a first cascode gain stage including a first complementary metal oxide semiconductor (“CMOS”) transistor configured to receive a radio frequency (“RF”) input signal and a second CMOS transistor coupled to an output node. The first inductive gate network is coupled to a gate of the second CMOS transistor for increasing a gain of the first cascode gain stage. The first inductive gate network has a non-zero inductive input impedance and includes at least one passive circuit element. | 02-09-2012 |
| 20120056769 | METHOD AND SYSTEM FOR TIME TO DIGITAL CONVERSION WITH CALIBRATION AND CORRECTION LOOPS - Methods and apparatuses for time to digital conversion (TDC) are disclosed. A timing circuit comprises a TDC circuit, a calibration module, and a correction module. The TDC circuit is configured to provide a timing signal indicative of a timing difference between edges of a periodic reference clock signal and a variable feedback signal. The TDC circuit is also configured to provide a delay signal that is variably delayed relative to the reference clock signal. The calibration module is configured to provide a calibration signal to increase and decrease a total delay of the TDC circuit based on a time delay of the calibration signal plus a time delay of a correction signal. The correction module, which is configured to receive the timing signal and provide the correction signal, minimizes harmonic spurs in a frequency response of the timing signal by operating at a frequency of the reference clock signal. | 03-08-2012 |
| 20120068745 | INJECTION-LOCKED FREQUENCY DIVIDER - A representative injection-locked frequency divider includes a differential direct injection pair that is configured to receive and mix differential injection signals and an oscillator that is electrically connected to the differential direct injection pair and produces an operating frequency based on the mixed differential injection signals. | 03-22-2012 |
Chewn-Pu Jou, Hsinchu TW
| Patent application number | Description | Published |
|---|---|---|
| 20110068766 | REFERENCE VOLTAGE GENERATORS, INTEGRATED CIRCUITS, AND METHODS FOR OPERATING THE REFERENCE VOLTAGE GENERATORS - A reference voltage generator includes a proportional to absolute temperature (PTAT) current source and a voltage divider. The PTAT current source is capable of providing a first current that is proportional to a temperature. The voltage divider is capable of receiving a second current that is proportional to the first current. The voltage divider is capable of outputting a reference voltage. The reference voltage is substantially independent from a change of the temperature. | 03-24-2011 |
| 20110090012 | CIRCUIT AND METHOD FOR RADIO FREQUENCY AMPLIFIER - A radio frequency amplifier circuit includes a substrate that is capable of receiving a substrate bias voltage. The source of a transistor is capable of receiving a source bias voltage. The drain of the transistor is capable of receiving a drain bias voltage. The gate of the transistor is located between the source and the drain. A radio frequency input signal is coupled to the gate. A substrate bias circuit provides the substrate bias voltage. The substrate bias voltage and the source bias voltage forward bias the first diode formed by the source and the substrate. The substrate bias voltage and the drain bias voltage reverse bias the second diode formed by the drain and the substrate. | 04-21-2011 |
| 20110108950 | VERTICAL METAL INSULATOR METAL CAPACITOR - A capacitor includes a first electrode. The first electrode includes a bottom conductive plane and a plurality of first vertical conductive structures. The bottom conductive plane is disposed over a substrate. The capacitor includes a second electrode. The second electrode includes a top conductive plane and a plurality of second vertical conductive structures. The capacitor includes an insulating structure between the first electrode and the second electrode. The first vertical conductive structures and the second vertical conductive structures are interlaced with each other thereby providing higher capacitance density. | 05-12-2011 |
| 20110193658 | FILTER USING A WAVEGUIDE STRUCTURE - A representative filter comprises a silicon-on-insulator substrate having a top surface, a metal shielding positioned above the top surface of the silicon-on-insulator substrate, and a band-pass filter device positioned above the metal shielding. The band-pass filter device includes a first port, a second port, and a coupling metal positioned between the first and second ports. | 08-11-2011 |
| 20110204969 | GATED-VARACTORS - Various embodiments of the invention provide a varactor structure that, depends on configurations, can provide a C-V characteristic based on one or a combination of a reverse bias junction capacitor, a channel capacitor, and an oxide capacitor. The junction capacitor is formed by reverse biasing the P+ source region and the N-well. The channel capacitance is formed between the P+ source region and the N+ drain region, and the oxide capacitor is formed in the gate oxide area. Depending on biasing one or a combination of the gate voltage VG, the source voltage VS, and the drain voltage VD, embodiments can utilize one or a combination of the above capacitors. Other embodiments using the varactors in a Voltage-Controlled Oscillator (VCO) are also disclosed. | 08-25-2011 |
| 20110215420 | CASCODE CMOS STRUCTURE - A MOS device includes an active area having first and second contacts. First and second gates are disposed between the first and second contacts. The first gate is disposed adjacent to the first contact and has a third contact. The second gate is disposed adjacent to the second contact and has a fourth contact coupled to the third contact. A transistor defined by the active area and the first gate has a first threshold voltage, and a transistor defined by the active area and the second gate has a second threshold voltage. | 09-08-2011 |
| 20120017192 | METHOD AND APPARATUS FOR LOW POWER SEMICONDUCTOR CHIP LAYOUT AND LOW POWER SEMICONDUCTOR CHIP - A layout system is described comprising a layout unit configured to layout cells in a mask design for a semiconductor chip based on library cells for a specified process node; a non-critical path determination unit configured to determine a non-critical path in the semiconductor chip; a cell determination unit configured to determine a group of cells in the mask design that form a part of the non-critical path and determine the corresponding library cell for at least one of the group of cells; a library cell modifying unit configured to modify one or more corresponding library cells to form a corresponding modified library cell; and a cell replacement unit configured to replace a library cell in the group of cells in the mask design that form a part of the non-critical path with the corresponding modified library cell. | 01-19-2012 |
| 20120068742 | METHOD AND APPARATUS FOR EFFICIENT TIME SLICING - Apparatus for efficient time slicing including a phase lock loop circuit having a voltage controlled oscillator, an auto-frequency calibration circuit coupled with the phase lock loop circuit configured to output a value to select a range of the voltage controlled oscillator, and a burst mode detector connected with the auto-frequency calibration circuit. The burst mode detector having a register adapted to store the output of the auto-frequency calibration circuit. | 03-22-2012 |
| 20120092077 | CAPACITOR COUPLED QUADRATURE VOLTAGE CONTROLLED OSCILLATOR - A quadrature oscillator includes a first oscillator having a first second-order harmonic node, a second oscillator having a second second-order harmonic node, and at least one capacitor coupling the first second-order harmonic node and the second second-order harmonic node. The first oscillator is configured to supply an in-phase signal and the second oscillator is configured to supply a quadrature signal. | 04-19-2012 |
| 20120092121 | BALANCED TRANSFORMER STRUCTURE - A multi-chip electronic device includes a first winding having a first port (P+) and a second port (P−). The first winding is formed in a metal layer of a first chip. The device further includes a second winding having a third (S+) and a fourth port (S−). The second winding is formed in a metal layer of a second chip. A center tap of the second winding is connected to a reference potential. | 04-19-2012 |
| 20120098592 | FILTER AUTO-CALIBRATION USING MULTI-CLOCK GENERATOR - A filter auto-calibration system includes a multi-clock module. The multi-clock module includes a multi-clock generator that is configured to generate a clock signal with a variable frequency based on a channel setting. There is at least one filter to be calibrated. An auto-calibration control module is configured to control calibration of the at least one filter based on the channel setting. The multi-clock module is configured to supply the variable frequency clock signal to the at least one filter and to the auto-calibration control module, and the at least one filter is coupled to the auto-calibration control module. | 04-26-2012 |
| 20120122395 | THROUGH CHIP COUPLING FOR SIGNAL TRANSPORT - Through-chip coupling is utilized for signal transport, where an interface is formed between a first coil on a first integrated circuit (IC) chip and a second coil on a second IC chip. The first coil is coupled to an antenna. The second coil is coupled to an amplifier circuit. The second coil is not in direct contact with the first coil. The first coil and the second coil communicatively transmit signals between the antenna and the first amplifier circuit. | 05-17-2012 |
Fan-Di Jou, Chiayi City TW
| Patent application number | Description | Published |
|---|---|---|
| 20110113079 | INFORMATION SWITCH MODULE AND RELATED FILE TRANSFER METHOD - An information switch module and a related file transfer method are disclosed. The information switch module is coupled to a first and a second host. The information switch module includes a switch and a storage device, and the switch includes at least a system controller, a first and a second USB controllers and an input device connection module. The system controller uses the storage device to simulate at least two USB mass storage device, and sets up an output storage space and an input storage space in the at least two USB mass storage devices, respectively. The first and second hosts access the output storage space and the input storage space through the first and second USB controllers, respectively. After the first host stores a file into the output storage space, the system controller provides a corresponding data of the file to the input storage space for the second host. | 05-12-2011 |
Fan-Di Jou, Taoyuan County TW
| Patent application number | Description | Published |
|---|---|---|
| 20090167866 | METHODS AND SYSTEMS FOR IMAGE PROCESSING IN A MULTIVIEW VIDEO SYSTEM - A system for image processing in a multiview video environment including a first camera and a second camera is disclosed. The system comprises a region of interest (ROI) module configured to receive first video signals from the first camera and detect at least one ROI in a first image related to the first video signals, a first lookup table configured to generate an attribute value in response to a type of a block, wherein the type of a block is related to a first vanishing point defined in the first image, a labeling module configured to identify a first point “p” most close to the first vanishing point, a second point “q” most remote to the first vanishing point and a length “h” between the first point “p” and the second point “q” in each of the at least one ROI, and generate first information on p, q and h, a second lookup table configured to generate second information on p′, q′ and h′ in response to the first information, wherein p′ is a first point most close to a second vanishing point defined in a second image related to the second camera, q′ is a second point most remote to the second vanishing point and h′ is a length between the first point p′ and the second point q′ in each of at least one ROI in the second image, and a transforming module configured to transform each of the at least one ROI in the first image into an ROI in the second image based on the second lookup table. | 07-02-2009 |
Geng-Shing Jou, Taoyuan County TW
| Patent application number | Description | Published |
|---|---|---|
| 20090245152 | POWER MANAGING METHOD APPLIED TO A WIRELESS NETWORK APPARATUS AND POWER MANAGEMENT THEREOF - A power managing method applied to a wireless network apparatus includes the steps of periodically detecting whether the wireless network apparatus is operated in a non-link status to determine whether to enter a first power-saving mode when the wireless network apparatus powered on; and determining the wireless network apparatus whether to enter a second power-saving mode according to an information of a beacon received by the wireless network apparatus when the wireless network apparatus is operated in a link status. When the wireless network apparatus is detected to be operated in the non-link status, control the wireless network apparatus to enter the first power-saving mode by a power mode controlling circuit. The first power-saving mode is an inactive power-saving mode, and the second power-saving mode is a linked power-saving mode. | 10-01-2009 |
Jau-Ji Jou, Taipei City TW
| Patent application number | Description | Published |
|---|---|---|
| 20100322624 | BIDIRECTIONAL TRANSMISSION NETWORK APPARATUS BASED ON TUNABLE RARE-EARTH-DOPED FIBER LASER - The present invention discloses a bidirectional transmission network apparatus based on a tunable rare-earth-doped fiber laser source. It is useful in wavelength-division-multiplexing access networks. The fiber ring laser not only generates downstream data traffic but also serves as the wavelength-selecting injection light source for the Fabry-Pérot lasers (or vertical cavity surface emitting lasers) located at the subscriber site. The fiber laser is constructed based on optical filtering, polarization control and noise suppression techniques. | 12-23-2010 |
Jing-Yang Jou, Hsin-Chu City TW
| Patent application number | Description | Published |
|---|---|---|
| 20080209093 | Fine-grained bandwidth control arbiter and the method thereof - A fine-grained bandwidth control arbiter manages the shared bus usage of the requests of the masters which have real-time and/or bandwidth requirements, moreover, the masters are preset a ticket respectively. The arbiter consists of three components, a real-time handler, a bandwidth regulator, and a lottery manager with tuned weight. The real-time handler grants the most urgent request. The bandwidth regulator handles the bandwidth allocation and blocks the requests of masters that have met the bandwidth requirement. The lottery manager with tuned weight stochastically grants one of the contending masters according to the ticket assignment. | 08-28-2008 |
Jing-Yang Jou, Hsinchu City TW
| Patent application number | Description | Published |
|---|---|---|
| 20110153709 | DELAY OPTIMAL COMPRESSOR TREE SYNTHESIS FOR LUT-BASED FPGAS - A compressor tree synthesis algorithm, named DOCT, which guarantees the delay optimal implementation in LUT-based FPGAs. Given a targeted K-input LUT architecture, DOCT firstly derives a finite set of prime patterns as essential building blocks. Then, it shows that a delay optimal compressor tree can always be constructed by those derived prime patterns via integer linear programming (ILP). Without loss of delay optimality, a post-processing procedure is invoked to reduce the number of demanded LUTs for the generated compressor tree design. DOCT has been evaluated over a broad set of benchmark circuits. The DOCT reduces the depth of the compressor tree and the number of LUTs based on the modern 8-input LUT-based FPGA architecture. | 06-23-2011 |
Jin-Long Jou, Kaohsiung City TW
| Patent application number | Description | Published |
|---|---|---|
| 20110160841 | MEDICAL APPLIANCE AND SURFACE TREATMENT METHOD THEREOF - A surface treatment method for a medical appliance is provided. The surface treatment method includes providing a metal layer; forming an intermediate layer on a surface of the metal layer, in which a thickness of the intermediate layer is greater than a thickness of a native oxide layer of the metal surface; and grafting a functional polymer on the intermediate layer through an electrodeposition process. | 06-30-2011 |
| 20120076847 | MEDICAL INSTRUMENT AND METHOD OF MANUFACTURING THE SAME - A medical instrument and a manufacturing method thereof are provided. The medical instrument includes a biomedical metal layer and a polymer film. The polymer film is a biodegradable polymer material. The manufacturing method includes the following steps: providing the biomedical metal layer, immersing the biomedical metal layer in a polymer solution, performing a baking process on the biomedical metal layer coated with a polymer film, forming the biomedical metal layer coated with the polymer film, taking out the biomedical metal layer coated with the polymer film to fabricate the medical instrument. The biodegradable polymer film and the biomedical metal layer are combined into the medical instrument, so that a physician performs a surgery more easily. In addition, decomposition time of the polymer film can be preset, so as to achieve efficacy of blocking soft tissue cells having a higher growth rate. | 03-29-2012 |
| 20120083882 | SPINAL IMPLANT STRUCTURE AND METHOD FOR MANUFACTURING THE SAME - A spinal implant structure includes a hollow cylinder and a biodegradable polymer membrane. The hollow cylinder is implanted in a bone damaged part of human vertebra. The biodegradable polymer membrane is formed to a part of a surface of the hollow cylinder. Thus, the biodegradable polymer membrane blocks invasion of soft tissues, and then the bone fillers integrated with vertebra are maintained without loss. | 04-05-2012 |
Jiun-Ying Jou, Taipei City TW
| Patent application number | Description | Published |
|---|---|---|
| 20110286390 | WIRELESS IMAGE TRANSMITTING APPARATUS AND METHOD FOR TRANSMITTING DATA THEREOF - A wireless image transmitting apparatus includes an image processing unit, a wireless bridging module, and a wireless local area network module. The wireless bridging module includes a network switch and a network port. The network switch is in signal communication with the network port and the image processing unit. The WLAN module is in signal communication with the network switch. The WLAN module uses a first type of packet and a first band to transmit a signal from the image processing unit and uses a second type of packet and a second band to transmit a signal from the network port. A method for transmitting data in a wireless image transmitting apparatus is also disclosed. | 11-24-2011 |
Jong-Dao Jou, Taipei TW
| Patent application number | Description | Published |
|---|---|---|
| 20100026565 | METHOD FOR GENERATING A REPRESENTATION OF AN ATMOSPHERIC VORTEX KINEMATIC STRUCTURE - A method for generating a representation of a kinematic structure of an atmospheric vortex is provided. The method comprises receiving a plurality of signals from a Doppler radar. The signals are reflected at a plurality of pulse volumes. The method also comprises measuring a plurality of Doppler velocities based on the received signals. A plurality of scaled Doppler velocities are calculated representing the plurality of measured Doppler velocities, the radial distance between the Doppler radar and the pulse volume where the Doppler velocity is measured, and the distance between the radar and a first estimated atmospheric vortex center. The method also comprises generating a representation of the kinematic structure of the atmospheric vortex using the plurality of scaled Doppler wind velocity values. | 02-04-2010 |
Jwo-Huei Jou, Hsinchu City TW
| Patent application number | Description | Published |
|---|---|---|
| 20110183454 | Method for preparing OLED by imprinting process - A method for preparing an OLED by an imprinting process is disclosed, which comprises the following steps: (A) providing a substrate, and a first electrode is formed thereon; (B) coating a mold with a first organic material ink; (C) pressing the mold coated with the first organic material ink on the substrate to transfer the first organic material ink onto the first electrode of the substrate, to obtain a first light-emitting array; (D) baking the substrate having the first light-emitting array formed thereon; and (E) forming a second electrode on the first light-emitting array. | 07-28-2011 |
Jwo-Huei Jou, Taipei City TW
| Patent application number | Description | Published |
|---|---|---|
| 20120008326 | Lighting Device Capable of Reducing the Phenomenon of Melatonin Suppression - According to research, it found that blue light may cause significant effects on suppressing melatonin. For this reason, a lighting device capable of reducing the phenomenon of melatonin suppression is disclosed in the present invention, the lighting device comprises: a light-emitting device being able to emit a visible light; and a light-filtering device being close to the light-emitting device, wherein when the light-emitting device emits the visible light, the light-filtering device is able to filter a blue light component of the visible light, so as to reduce the blue light component within the visible light emitted by the light-emitting device, then the effects on suppressing the melatonin caused by the visible light are reduced. | 01-12-2012 |
Jwo-Huei Jou, Taipei TW
| Patent application number | Description | Published |
|---|---|---|
| 20100300520 | PHOTOVOLTAIC CELL HAVING NANODOTS AND METHOD FOR FORMING THE SAME - The present invention provides a photovoltaic cell comprising a photovoltaic conversion layer and a pair of electrodes. The photovoltaic conversion layer, being capable of converting incident light into a plurality hole-electron pairs, comprises a hole transport layer including a plurality of nanodots mixed therein for transporting the holes generated from the photovoltaic effect. The pair of electrodes are coupled respectively to two sides of the photovoltaic conversion layer for conducting holes and electrons. In another embodiment, the present invention further provides a method for forming the photovoltaic cell, wherein the nanodots are mixed in a solution formed of a hole transport material and then a hole transport layer having the nanodots is formed on a conductive substrate. In the photovoltaic cell having nanodots of the present invention, the hole mobility is enhanced so as to improve the efficiency of the photovoltaic cell. | 12-02-2010 |
| 20110316443 | ILLUMINATING APPARATUS AND ILLUMINATING METHOD THEREOF - The present invention discloses an illuminating apparatus and an illuminating method thereof. The illuminating apparatus comprises a first electrode, a first organic light emitting diode, a second electrode, a second organic light emitting diode and a third electrode. The first and second organic light emitting diodes emit lights with a first chromaticity and a second chromaticity respectively. The illuminating apparatus further comprises a control module, and the control module can supply a first voltage, a second voltage and a third voltage to the first, second and third electrodes so as to emit a sun-like light and adjust the color temperature or the brightness of the light. | 12-29-2011 |
Jwo-Huei Jou, Hsinchu TW
| Patent application number | Description | Published |
|---|---|---|
| 20100051997 | Organic light emitting diode and method of fabricating the same - The present invention discloses an organic light emitting diode and a method of fabricating the organic light emitting diode. The OLED device includes one or more light emitting layers, and the light emitting layer is composed of one or more light emitting materials and one or more subject materials, and the subject material has a molecular polarity different from the molecular polarity of the light emitting material, such that the light emitting molecules can be self dispersed to emit a darker blue light color or a light color of a longer wavelength. | 03-04-2010 |
| 20100051998 | Organic light emitting diode and method of fabricating the same - The present invention discloses an organic light emitting diode and a method of fabricating the organic light emitting diode. The OLED device includes one or more light emitting layers, and the light emitting layer is composed of one or more light emitting materials and one or more subject materials, and the subject material has a molecular polarity different from the molecular polarity of the light emitting material, such that the light emitting molecules can be self dispersed to emit a more reddish light color or a light color of a longer wavelength. | 03-04-2010 |
| 20110111552 | Method for forming organic layers of electronic devices by contact printing - A method for forming organic layers of electronic devices by contact printing is disclosed, which comprises: (A) providing a substrate, which has an electrode formed thereon; (B) coating an organic material ink onto a mold; (C) applying the ink-coated mold onto the substrate, to transfer the organic material ink onto the electrode of the substrate and then to form an organic layer; and (D) forming another electrode on the organic layer. In addition, after the step (C) is completed, the steps (B) to (C) can be repeated once or several times to form series of organic layers, if needed. | 05-12-2011 |
| 20110240963 | ORGANIC LIGHT-EMITTING DIODE WITH HIGH COLOR RENDERING - An organic light-emitting diode with high color rendering is provided, which comprises: a substrate with a first electrode formed thereon; a first light-emitting region disposed over the first electrode, wherein the first light-emitting region comprises at least one layer of a first light-emitting layer, and the first light-emitting layer comprises at least one first dye respectively; a spacer disposed on the first light-emitting region; a second light-emitting region disposed on the organic spacer, wherein the second light-emitting region comprises at least one layer of a second light-emitting layer, and the second light-emitting layer comprises at least one second dye respectively; and a second electrode disposed over the second light-emitting region. | 10-06-2011 |
| 20110254033 | Organic Light-Emitting Diode Device with High Color Rendering - The present invention discloses an organic light-emitting diode (OLED) device with high color rendering comprising a base plate, a first conductive layer, a plurality of white light emitting layers, and a second conductive layer, wherein the spectra of the white light emitting layers possess characteristics of complementarities so as to enhance the color rendering of the emitted white light, and at least one carrier regulating layer is selectively disposed between every two white light emitting layers so as to increase the emitting efficiency and color rendering. | 10-20-2011 |
| 20110303902 | ORGANIC LIGHT-EMITTING DIODE WITH HIGH COLOR RENDERING - An organic light-emitting diode with high color rendering is provided, which includes: a substrate; a first electrode disposed over the substrate; a light-emitting region disposed over the first electrode, in which the light-emitting region includes a plurality of light-emitting layers and at least one spacer, the spacer being disposed between any two of the light-emitting layers and each of the light-emitting layers individually including a dye; and a second electrode disposed over the light-emitting region. Accordingly, the organic light-emitting diode according to the present invention can exhibit high color rendering and high illumination efficiency. | 12-15-2011 |
| 20120032153 | Organic Light-Emitting Diode Device - The present invention relates to an improved organic light-emitting diode (OLED) device which comprises a first conductive layer, a first light-emitting material layer, a second light-emitting material layer, a second conductive layer, and at least one third light-emitting material layer, wherein the first conductive layer is adapted for being an anode substrate, moreover, by way of evaporation process, the first light-emitting material layer, the third light-emitting material layer, the second light-emitting material layer, and the second conductive layer are formed on the anode substrate in turns. Besides, the phenomenon of efficiency roll-off occurring in a high luminance region of the OLED device may be improved by adding the third light-emitting material layer between the first light-emitting material layer and the second light-emitting material layer. | 02-09-2012 |
Jwo-Ming Jou, Kaohsiung City TW
| Patent application number | Description | Published |
|---|---|---|
| 20100073787 | PIEZOELECTRIC-DRIVING OPTICAL LENS - A piezoelectric-driving optical lens is disclosed, which comprises: a lens, having a barrel with a friction ring annularly mounted on the outer wall of the barrel as the outer diameter of the friction ring is larger than that of the barrel; a plurality of piezoelectric stators, arranged surrounding the lens and abutted against the friction ring, for providing a rotation driving force to the lens for focusing or zooming function; and a seat, for receiving the lens and the plural piezoelectric stators; wherein, the plural piezoelectric stators can actuate simultaneously to output a maximum driving torque. | 03-25-2010 |
Leng-Long Jou, Sanchong City TW
| Patent application number | Description | Published |
|---|---|---|
| 20100152374 | FLAME-RETARDANT WATERBORNE POLYURETHANE DISPERSION - The invention provides a flame-retardant waterborne polyurethane dispersion. The dispersion includes: 1 to 15 parts by weight of a phosphorus flame retardant containing active hydrogen; 10 to 40 parts by weight of a diisocyanate; 30 to 80 parts by weight of a polyol; and 1 to 15 parts by weight of an active hydrogen-containing compound, which is capable of forming a hydrophilic group. | 06-17-2010 |
Li-Pin Jou, Hsinchu TW
| Patent application number | Description | Published |
|---|---|---|
| 20100029035 | METHOD OF MANUFACTURING A PHOTOELECTRONIC DEVICE - This application discloses a method of manufacturing a photoelectronic device comprising steps of providing a semiconductor stack layer, forming at least one metal adhesive on the semiconductor stack layer by a printing technology, forming an electrode by heating the metal adhesive to remove the solvent in the metal adhesive, wherein an ohmic contact is formed between the electrode and the semiconductor stack layer. | 02-04-2010 |
Li-Ping Jou, Hsinchu TW
| Patent application number | Description | Published |
|---|---|---|
| 20110227120 | LIGHT-EMITTING DEVICE - A light-emitting device comprises a substrate, an epitaxial structure formed on the substrate including a first semiconductor layer, a second semiconductor layer, and a light-emitting layer formed between the first semiconductor layer and the second semiconductor layer. A trench is formed in the epitaxial structure to expose a part of side surface of the epitaxial structure and a part of surface of the first semiconductor layer, so that a first conductive structure is formed on the part of surface of the first semiconductor layer in the trench, and a second conductive structure is formed on the second semiconductor layer. The first conductive structure includes a first electrode and a first pad electrically contacted with each other. The second conductive structure includes a second electrode and a second pad electrically contacted with each other. Furthermore, the area of at least one of the first pad and the second pad is between 1.5×10 | 09-22-2011 |
Ming-Jiunn Jou, Hsinchu TW
| Patent application number | Description | Published |
|---|---|---|
| 20110220873 | LIGHT EMITTING DIODE HAVING A TRANSPARENT SUBSTRATE - A light emitting diode having a transparent substrate and a method for manufacturing the same. The light emitting diode is formed by creating two semiconductor multilayers and bonding them. The first semiconductor multilayer is formed on a non-transparent substrate. The second semiconductor multilayer is created by forming an amorphous interface layer on a transparent substrate. The two semiconductor multilayers are bonded and the non-transparent substrate is removed, leaving a semiconductor multilayer with a transparent substrate. | 09-15-2011 |
Ming-Jong Jou, Hsinchu TW
| Patent application number | Description | Published |
|---|---|---|
| 20090102764 | Liquid Crystal Display and Driving Method Therefor - A liquid crystal display is provided. The liquid crystal display includes a substrate, a plurality of data lines, a plurality of gate lines, a gate driving circuit, and a source driving circuit. The substrate includes a pixel array including a plurality of pixels arranged as a matrix. The data lines are electrically connected to the pixel array. The gate lines are electrically connected to the pixel array and include a plurality of odd-numbered gate lines and a plurality of even-numbered gate lines, wherein one of the odd-numbered gate lines and one of the even-numbered gate lines are electrically connected to the pixels located in the same row. The gate driving circuit includes a first gate driving circuit and a second gate driving circuit, wherein the first gate driving circuit is electrically connected to the odd-numbered gate lines and the second gate driving circuit is electrically connected to the even-numbered gate lines. The source driving circuit is electrically connected to the data lines. | 04-23-2009 |
| 20100039405 | Projective Capacitive Touch Apparatus, and Method for Identifying Distinctive Positions - A projective capacitive touch apparatus and a method for identifying multi-touched positions are provided. The multi-touched positions are touched on a projective capacitive touch panel. The method comprises the following steps: generating a first set of reference values according to the first touch position; generating a plurality of second sets of reference values according to a second touch position, and filtering out at least one ghost second set of reference values from the second sets of reference values. Furthermore, the plurality of second sets of reference values comprise a real second set of reference value and at least one ghost second set of reference values, while the ghost second set of reference values comprises parts of the first set of reference values. | 02-18-2010 |
Rong-Yuan Jou, Da Li City TW
| Patent application number | Description | Published |
|---|---|---|
| 20090175006 | HONEYCOMB HEAT DISSIPATING APPARATUS - A honeycomb heat dissipating apparatus made of a composite metal material includes honeycomb cells that are integrally formed by vacuum die casting, and continuous convex and concave distal surfaces disposed around the periphery of the heat dissipating apparatus, and an adjacent surface of each cell is a thin surface, and the heat dissipating apparatus can be in a standalone mode, or combined with other heat dissipating apparatuses. One or more honeycomb heat dissipating apparatuses can be installed on a circuit board or an electronic component of a lamp or an electric appliance, such that the heat dissipating apparatus can dissipate heat quickly by the honeycomb cells without occupying much space. The invention can increase the heat dissipating area for a faster heat dissipating effect and change the stylish appearance to achieve the aesthetic effect. | 07-09-2009 |
Ruwen Jou, Taipei City TW
| Patent application number | Description | Published |
|---|---|---|
| 20080261221 | AUTOMATED VNTR GENOTYPING METHOD - The invention provides an automated VNTR genotyping method using multiple variable-number tandem repeats (VNTRs) loci based on mycobacterial interspersed repetitive units (MIRU) undergoing multiplex PGR and high throughput MEGABACE® capillary electrophoresis system. The method uses fluorescent dyes of 6-carboxytetramethylrhodamine(TAMRA), 6-carboxy fluorescein (FAM) and 6-carboxy-2′, 4, 4′, 5′, 7, 7′-hexachlorofluorescein (HEX) labeling PGR primers. The method results in an efficient VNTR genotyping with low cost, less labor-requirement and less reaction time. The method is applicable in organism analyses by VNTR genotyping, such as microorganisms, parasites, animals or plants. | 10-23-2008 |
Shin-Hung Jou, Changhua County TW
| Patent application number | Description | Published |
|---|---|---|
| 20090282177 | APPARATUS AND METHOD FOR SIGNAL TRANSMISSION IN EMBEDDED SYSTEM - An apparatus and a method for signal transmission in an embedded system. The apparatus comprises: a master control chip, embedded in the embedded system and comprising a controller and a plurality of I/O pins; a plurality of slave chips; and a bus having one end coupled to the plurality of I/O pins and the other end coupled to one of the plurality of slave chips; wherein data or signals are bi-directionally transmitted. The method comprises steps of: transmitting a control signal from a master control chip to a slave chip; starting an operation by the slave chip after receiving the control signal; transmitting a data signal and a command signal to the master control chip from the slave chip; processing the data signal according to the command signal by the master control chip; and transmitting another control signal from the master control chip to the slave chip to terminate the operation. | 11-12-2009 |
Shyan-Kay Jou, Taipei County TW
| Patent application number | Description | Published |
|---|---|---|
| 20110132745 | METHOD OF FABRICATING VARIABLE RESISTANCE LAYER FOR RESISTANCE MEMORY - A method of fabricating a variable resistance layer of a resistance memory is disclosed. The method includes placing a substrate in a sputtering chamber that has a copper target and a silicon oxide (SiO | 06-09-2011 |
Shyan-Kay Jou, Taipei City TW
| Patent application number | Description | Published |
|---|---|---|
| 20090087567 | METHOD OF FABRICATING ONE-DIMENSIONAL METALLIC NANOSTRUCTURE - A method of fabricating one-dimensional metallic nanostructure is provided. First, a mixing layer including a first oxide and a second oxide is provided. The first oxide is a metallic oxide, and the first oxide and the second oxide are immiscible. Next, a reducing gas is introduced and a thermal process is performed on the mixing layer so as to reduce the metal of the first oxide to form one-dimensional metallic nanostructure. | 04-02-2009 |
Shyh-Jye Jou, Baoshan Township TW
| Patent application number | Description | Published |
|---|---|---|
| 20110235444 | SRAM WRITING SYSTEM AND RELATED APPARATUS - SRAM writing system and related apparatus are provided. The writing system of the invention has a dummy replica writing circuit, a negative pulse controller and at least a normal writing circuit; each normal writing circuit includes a write driver and a negative pulse supplier. While writing, the dummy replica writing circuit drives a dummy replica bit-line, such that the negative pulse controller generates a negative pulse control signal according to level of the dummy replica bit-line. In each writing circuit, when the write driver conducts to connect an associated bit-line to a bias end for driving a level transition, the negative pulse supplier switches the bias end from an operation voltage to a different negative pulse voltage according to the received negative pulse control signal. | 09-29-2011 |
Shyh-Jye Jou, Hsinchu County TW
| Patent application number | Description | Published |
|---|---|---|
| 20110128796 | DISTURB-FREE STATIC RANDOM ACCESS MEMORY CELL - A disturb-free static random access memory cell includes: a latch circuit having a first access terminal and a second access terminal; a first switching circuit having a first bit transferring terminal coupled to the first access terminal, a first control terminal coupled to a first write word line, and a second bit transferring terminal; a second switching circuit having a third bit transferring terminal coupled to the second access terminal, a second control terminal coupled to a second write word line, and a fourth bit transferring terminal coupled to the second bit transferring terminal; a third switching circuit having a fifth bit transferring terminal coupled to the fourth bit transferring terminal, a third control terminal coupled to a word line, and a sixth bit transferring terminal coupled to a bit line; and a sensing amplifier coupled to the bit line, for determining a bit value appearing at the bit line. | 06-02-2011 |
| 20120008377 | STATIC RANDOM ACCESS MEMORY WITH DATA CONTROLLED POWER SUPPLY - A static random access memory with data controlled power supply, which comprises a memory cell circuit and at least one Write-assist circuit, for providing power to the memory cell circuit according to data to be written to the memory cell circuit. | 01-12-2012 |
| 20120057399 | ASYMMETRIC VIRTUAL-GROUND SINGLE-ENDED SRAM AND SYSTEM THEREOF - The present invention discloses an asymmetric virtual-ground single-ended SRAM and a system thereof, wherein a first inverter is coupled to a high potential and a virtual ground, and wherein the first inverter and a second inverter form a latch loop, and wherein a third inverter is electrically connected with the second inverter, and wherein the third inverter and the second inverter are jointly coupled to the high potential and a ground. A write word line and a read word line control an access transistor and a pass transistor to undertake writing and reading of signals. A plurality of asymmetric virtual-ground single-ended SRAMs forms a memory system. | 03-08-2012 |
Wan-Chen Jou, Banciao City TW
| Patent application number | Description | Published |
|---|---|---|
| 20090025125 | Diving goggles with defogging device - A diving goggles with defogging device, including a flexible frame provided with an adjustable fastening strap that is used to secure the diving goggles to the face of a user; an exterior lens used to seal off sea water from flowing into the flexible frame is fixed to the extreme exterior of the flexible frame; an internal lens which forms an airtight interlayer with the exterior lens is fixed to an inner side of the flexible frame; and a heating element used to maintain temperature of the internal lens is disposed on the internal lens. Accordingly, the present invention is able to effectively prevent fogging from occurring because of the temperature difference between body heat from the user and the lenses of the goggles. | 01-29-2009 |
Wen-Hann Jou, Taipei County TW
| Patent application number | Description | Published |
|---|---|---|
| 20090105112 | Nono-clay composite and composition for fabricating the same - The present invention relates to a nano-clay composite and a composition for fabricating the same. The nano-clay composite of the invention is formed by compounding a composition comprising a polymer, a surfactant, a polymer modification component, and micro/nano powders. The nano-clay composite is flexible to completely adhere to cleaning surfaces to remove unwanted materials via the release of surfactant, as well as the scrubbing effect produced by the friction between micro/nano powders and the surface. | 04-23-2009 |
Wern-Shiarng Jou, Kaohsiung TW
| Patent application number | Description | Published |
|---|---|---|
| 20100275393 | METHOD OF MAKING A LASTED SKATE BOOT - A method of making a lasted skate boot comprising: (a) providing a male-female mold having male and female sections for defining a mold cavity therebetween, the male section having sides, a rear portion and a bottom portion for defining a three dimensional shape corresponding to the external three dimensional shape of the foot, the female section defining a recess for receiving the male section, the male section comprising a plurality of inner channels for admitting liquid plastic material in the mold cavity; (b) providing a pre-cut sheet made of cloth material laminated to a support made of non-woven fabric; (c) placing the sheet on the male section of the mold such that the non-woven fabric contacts the sides and rear portion of the male section of the mold; (d) closing the male and female sections of the mold; (e) injecting liquid plastic material in the inner channels such that the liquid plastic material spreads on the sheet, pushes the sheet against the recess of the female section of the mold, fills the mold cavity and fuses with the non-woven fabric to form, after cooling, an outer shell comprising a heel portion for surrounding the heel, an ankle portion for surrounding the ankle, and medial and lateral side portions for enclosing the medial and lateral sides of the foot respectively; (f) opening the male and female sections of the mold; and (g) removing the outer shell from the mold. | 11-04-2010 |
Wuu-Cheau Jou, Dali City TW
| Patent application number | Description | Published |
|---|---|---|
| 20080276480 | RACK FOR DRIERS - A rack for driers includes a support with a Y-axis tube set connected thereto and an inlet unit is mounted to the Y-axis tube set so that two connection members are respectively connected thereto. A Z-axis tube is connected to a vertical sleeve unit on the Y-axis tube set and an X-axis tube is connected to a horizontal sleeve unit on the Z-axis tube. Two driers are connected to two drier bases on the X-axis tube. The two driers are connected to the two connection members by hoses. The positions of the driers are adjusted in three directions and the inlet unit is rotated about the Y-axis tube set. | 11-13-2008 |
Wuu-Cheau Jou, Taichung Hsien TW
| Patent application number | Description | Published |
|---|---|---|
| 20080230626 | SIPHON DRYING GUN - A siphon type of drying gun includes an arc diverter disposed between an inner end surface in an accommodation space in a body of the gun and a flared hole. A rear cover having a flange is screwed into the body. An exhaustion gap is defined between the flange of the rear cover and the arc diverter. A front tapered hole in the rear cover corresponding to the arc diverter to guide the compressed air admitted into the exhaustion gap to flow by following the arc diverter and taking a turn into the flared hole so to produce siphon effects against ambient air to reduce noise level. | 09-25-2008 |
| 20080283699 | STAND FOR A DRYING GUN SUPPORTING FRAME - A stand for a drying gun supporting frame includes a body and a socket at 90 degrees to the body. A spherical valve is disposed in the body, and a connecting unit is provided at the top of the body. The socket has a threaded hole at one side to receive a manual screw therein so as to secure a balancing pipe thereat. The spherical valve disposed in the body comprises a ball, washers, a cap and a linking rod. The altitude of the spherical valve is lower than the center of the balancing pipe, which lowers the outlet of the drying gun and provides a steady operation of the drying gun. | 11-20-2008 |
Yeh-Ning Jou, Taipei County TW
| Patent application number | Description | Published |
|---|---|---|
| 20090135532 | ELECTROSTATIC DISCHARGE PROTECTION CIRCUITS - An electrostatic discharge (ESD) protection circuit is provided. A transistor is coupled between a node and a ground, and has a gate coupled to the ground. A diode chain is coupled between the node and a pad, and comprises a plurality of first diodes connected in series, wherein the first diode is coupled in a forward conduction direction from the pad to the node. A second diode is coupled between the node and the pad, and the second diode is coupled in a forward conduction direction from the node to the pad. | 05-28-2009 |
| 20090140370 | SEMICONDUCTOR DEVICE - A semiconductor device is described. The semiconductor device comprises a protected device in a protected device area of a substrate. An electrostatic discharge power clamp device comprising an outer first guard ring and an inner second guard ring is in a guard ring area of the substrate, enclosing the protected device. The first guard ring comprises a first well region having a first conductive type. A first doped region having the first conductive type and a second doped region having a second conductive type are in the first well region. The second guard ring comprises a second well region having a second conductive type. A third doped region has the second conductive type in the second well region. An input/output device is in a periphery device area, coupled to the electrostatic discharge power clamp device. | 06-04-2009 |
| 20090261417 | TRIG MODULATION ELECTROSTATIC DISCHARGE (ESD) PROTECTION DEVICES - Trig modulation electrostatic discharge (ESD) protection devices are presented. An ESD protection device includes a semiconductor substrate. A high voltage N-well (HVNW) region is formed in the semiconductor substrate. An NDD region, a first P-body region and a second P-body region are formed in the HVNW region, wherein the first P-body region is separated from the second P-body region with a predetermined distance, and wherein the NDD region is isolated from the first P-body region with an isolation region. An N | 10-22-2009 |
| 20100187566 | INSULATED GATE BIPOLAR TRANSISTOR (IGBT) ELECTROSTATIC DISCHARGE (ESD) PROTECTION DEVICES - Insulated gate bipolar transistor (IGBT) electrostatic discharge (ESD) protection devices are presented. An IGBT-ESD device includes a semiconductor substrate and patterned insulation regions disposed on the semiconductor substrate defining a first active region and a second active region. A high-V N-well is formed in the first active region of the semiconductor substrate. A P-body doped region is formed in the second active region of the semiconductor substrate, wherein the high-V N-well and the P-body doped region are separated with a predetermined distance exposing the semiconductor substrate. A P | 07-29-2010 |
| 20100208398 | ELECTROSTATIC DISCHARGE PROTECTION CIRCUIT AND INTEFRATED CIRCUIT UTILIZING THE SAME - An ESD protection circuit coupled between a first power line and a second power line to avoid damage to an integrated circuit by an ESD event is disclosed. The ESD protection circuit includes a detection unit, a trigger unit, and a discharging unit. The detection unit asserts a detection signal when the ESD event occurs. The trigger unit asserts a first trigger signal and a second trigger signal when the detection is asserted. The discharging unit provides a discharge path to release an ESD current caused by the ESD event when the first and the second trigger signals are asserted. | 08-19-2010 |
| 20110012204 | TRIG MODULATION ELECTROSTATIC DISCHARGE (ESD) PROTECTION DEVICES - Trig modulation electrostatic discharge (ESD) protection devices are presented. An ESD protection device includes a semiconductor substrate. A high voltage N-well (HVNW) region is formed in the semiconductor substrate. An NDD region, a first P-body region and a second P-body region are formed in the HVNW region, wherein the first P-body region is separated from the second P-body region with a predetermined distance, and wherein the NDD region is isolated from the first P-body region with an isolation region. An N | 01-20-2011 |
| 20120001225 | INSULATED GATE BIPOLAR TRANSISTOR (IGBT) ELECTROSTATIC DISCHARGE (ESD) PROTECTION DEVICES - Insulated gate bipolar transistor (IGBT) electrostatic discharge (ESD) protection devices are presented. An IGBT-ESD device includes a semiconductor substrate and patterned insulation regions disposed on the semiconductor substrate defining a first active region and a second active region. A high-V N-well is formed in the first active region of the semiconductor substrate. A P-body doped region is formed in the second active region of the semiconductor substrate, wherein the high-V N-well and the P-body doped region are separated with a predetermined distance exposing the semiconductor substrate. A P | 01-05-2012 |
| 20120056239 | ELECTROSTATIC DISCHARGE PROTECTION DEVICE - An electrostatic discharge protection device is coupled between a first power line and a second power line and comprises a P-type well, a first N-type doped region, a first P-type doped region, a second P-type doped region and a second N-type doped region. The first N-type doped region is formed in the P-type well. The first P-type doped region is formed in the first N-type doped region. The second P-type doped region comprises a first portion and a second portion. The first portion of the second P-type doped region is formed in the first N-type doped region. The second portion of the second P-type doped region is formed outside of the first N-type doped region. The second N-type doped region is formed in the first portion of the second P-type doped region. The first P-type doped region, the first N-type doped region, the second P-type doped region and the second N-type doped region constitute an insulated gate bipolar transistor (IGBT). | 03-08-2012 |
Yen-Pong Jou, Taoyuan County TW
| Patent application number | Description | Published |
|---|---|---|
| 20100161509 | INTELLECTUAL PROPERTY MANAGEMENT METHOD AND INTELLECTUAL PROPERTY BANK SYSTEM - An intellectual property management method and an intellectual property bank system are provided. The intellectual property management method includes raising funds to set up a fund company by a plurality of members to purchase intellectual properties. The intellectual property management method also includes setting up an intellectual property management company to assist purchasing and managing the purchased intellectual properties of the fund company. The intellectual property management method further includes selling the intellectual properties to the members when a special event occurs to the members such that the members can own the intellectual properties to deal with the special event. Therefore, the intellectual property management method can provide the members with powerful protection with fewer resources and lower costs. | 06-24-2010 |
Yow-Jen Jou, Hsinchu City TW
| Patent application number | Description | Published |
|---|---|---|
| 20100161204 | Method for identification of traffic lane boundary - The invention provides a method for identification of traffic lane boundary. Firstly the microwave signal is received, and the noise reduction is treated for the microwave signal. Then the frequency domain information is employed to calculate the legal set of closed interval, in order to form the frequency span information. Finally, the probability density function model is employed to calculate the frequency span information in order to identify the traffic lane boundary. | 06-24-2010 |
Yuh-Shan Jou, Taipei TW
| Patent application number | Description | Published |
|---|---|---|
| 20120129869 | PHOSPHORYLATION AND MUTATIONS OF ANAPLASTIC LYMPHOMA KINASE AS A DIAGNOSTIC AND THERAPEUTIC TARGET IN LUNG CANCER - The invention related to the use of high-density loss of heterozygosity (LOH) mapping in lung adenocarcinoma to identify intragenic LOH and driver mutations in different domains of ALK resulted in enhanced tumor growth in xenografted mouse. Mutant (H694R and E1384K) ALKs showed activation of Y1604 ALK and downstream AKT, STAT3 and ERK signaling pathways. Increases of oncogenic signalings resulted in enhanced cell proliferation, colony-formation, cell-migration and tumor-growth in xenografted mouse. Western blot and immunohistochemistry analysis using antibody against phospho-Y1604 ALK on 11 lung cancer cell-lines and 263 cancer specimens indicated ALK activation in all lung cancers regardless of tumor stages. Treating mutant-bearing mice with ALK inhibitor WHI-P 154 resulted in tumor shrinkage, metastasis suppression, and improved survival. Hyperphosphorylation of Y1604 ALK occurred early and continuously throughout tumor progression and could be used as a biomarker to detect lung cancer. Oncogenic ALK point mutations could be treatment targets for lung cancer. | 05-24-2012 |
Yung-Tsan Jou, Taoyuan County TW
| Patent application number | Description | Published |
|---|---|---|
| 20100320261 | DUAL-PURPOSE FOOD CONTAINER - A dual-purpose food container includes a first bowl body, a second bowl body, and a tear portion. The first bowl body has a first opening, is made of a first heat-insulating material, and is used for accommodating contents. The second bowl body has a second opening and is made of a second heat-insulating material, in which the second opening faces the first opening such that the second bowl body covers the first bowl body and the second bowl body is connected to the first bowl body. The tear portion is located at a connection position between the first bowl body and the second bowl body, and the tear portion is torn to separate the first bowl body from the second bowl body, so that the first bowl body and the second bowl body are respectively used to serve food and soup, thereby achieving a dual purpose. | 12-23-2010 |
| 20110049225 | FOOD CONTAINER - A food container includes a bowl body, a first cover, a first tear portion, and an eating utensil. The bowl body has a first opening, is made of a first heat-insulating material, and is used for accommodating contents. The first cover is made of a second heat-insulating material, and covers the bowl body, in which the first cover is connected to the bowl body, and includes a sealing portion for placing an additive into the bowl body. The first tear portion is located at a connection position between the bowl body and the first cover, and the first tear portion is torn to separate the bowl body from the first cover. The eating utensil is located at the first cover. | 03-03-2011 |
Yu-Tang Jou, Sanchung TW
| Patent application number | Description | Published |
|---|---|---|
| 20100122433 | Rotating mechanism for an electronic device and an electronic device with the same - A rotating mechanism for an electronic device has a stationary seat with a limiting recess, a limiting ring mounted through the stationary seat with inner and outer limits, a shaft mounted through the stationary seat and the limiting ring with a limiting protrusion. With the limiting protrusion pushing the inner limit and the outer limit sliding in the limiting recess, the shaft achieves two stages of rotation to enhance the rotating angle in both directions. Moreover, with the adjusting of the sizes of the components, the rotating mechanism may provide rotating angle by 360 to 700 degrees. | 05-20-2010 |
Zuei-Chown Jou, Taipei City TW
| Patent application number | Description | Published |
|---|---|---|
| 20090153273 | ENERGY TRANSFERRING SYSTEM AND METHOD THEREOF - An energy transferring system including a source-side resonator, an intermediate resonant module, and a device-side resonator is provided. The three resonators substantially have the same resonant frequency for generating resonance. The energy on the source-side resonator is coupled to the intermediate resonant module, such that non-radiative energy transfer is performed between the source-side resonator and the intermediate resonant module. The energy coupled to the intermediate resonant module is further coupled to the device-side resonator, such that non-radiative energy transfer is performed between the intermediate resonant module and the device-side resonator to achieve energy transfer between the source-side resonator and the device-side resonator. The coupling coefficient between the intermediate resonant module and its two adjacent resonators is larger than the coupling coefficient between the source-side resonator and the device-side resonator. The invention has the advantages of high transmission efficiency, small volume, low cost. | 06-18-2009 |