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Joshi, OR
Ajit Joshi, Portland, OR US
| Patent application number | Description | Published |
|---|---|---|
| 20090087162 | Method and apparatus for media playback - In one embodiment of the invention, a memory may receive digital video data containing a first I frame and a second I frame with a plurality of P frames located between the I frames. The I frames each include a first timestamp. A processor may determine a subset of the P frames to be played in a trick mode along with the first I frame and the second I frame based on the number of P frames included in the plurality of P frames and the desired playback speed. | 04-02-2009 |
Ajit P. Joshi, Portland, OR US
| Patent application number | Description | Published |
|---|---|---|
| 20090013358 | Distributed video recording and playback - A method may include receiving a recording request for media information from a first media system. The method may also include selecting a source of the media information and selecting a storage destination for the media information. Recording and/or playback of the media information from the source to the storage destination may be scheduled. | 01-08-2009 |
| 20100169502 | Hybrid method for delivering streaming media within the home - A hybrid system and method for delivering “streaming” media within the home. According to the method, small portions of media items from a controlling device are received at a rendering device for pre-caching into a cache. Upon a user selecting a media item for playback, play of the media item is immediately started from the cache in real-time while the remaining portions of the selected media item are downloaded from the controlling device and appended to cache at a rate faster than real-time. | 07-01-2010 |
| 20110069835 | Method and apparatus for allowing software access to navigational data in a decrypted media stream while protecting stream payloads - A method, apparatus and system enabling software access to navigational data in a decrypted media stream while protecting stream payloads. In one embodiment, a filter may route an encrypted content stream and associated information to a secure partition having a trusted computing component for decryption. Upon decryption, the trusted computing component may store the decrypted payload of the content in a secure storage location accessible to the trusted computing component. Thereafter, the decrypted navigational header information of the content may be used to navigate to the decrypted content via a trusted component such as a trusted rendering unit in the secure partition. | 03-24-2011 |
Dhananjay Joshi, Beaverton, OR US
| Patent application number | Description | Published |
|---|---|---|
| 20080235461 | Technique and apparatus for combining partial write transactions - A bridge includes a memory to establish a transaction table and write combining windows. Each write combining window is associated with a cache line and is subdivided into subwindows; and each of the subwindows is associated with a partial cache line. The bridge includes a controller to determine whether an incoming partial write transaction conflicts with a transaction stored in the transaction table. If a conflict occurs, the controller uses the write combining windows to combine the partial write transaction with another partial write transaction if one of the partial write combining windows is available. The controller issues a retry signal to a processor originating the partial write transaction if none of the partial write combining windows are available. | 09-25-2008 |
Mandar Joshi, Portland, OR US
| Patent application number | Description | Published |
|---|---|---|
| 20080233962 | TECHNIQUES FOR ALWAYS ON ALWAYS CONNECTED OPERATION OF MOBILE PLATFORMS USING NETWORK INTERFACE CARDS - An embodiment of the present invention provides an apparatus, comprising a network interface (NIC) card operable in communication with a mobile platform to monitor network traffic and perform filtering to enable decreased system resource use in said mobile platform when in an Always On Always Connected (AOAC) state. | 09-25-2008 |
| 20100235504 | METHOD AND APPARATUS FOR A POWER-EFFICIENT FRAMEWORK TO MAINTAIN DATA SYNCHRONIZATION OF A MOBILE PERSONAL COMPUTER TO SIMULATE A CONNECTED SCENARIO - An apparatus and method for a power-efficient framework to maintain data synchronization of a mobile personal computer (MPC) are described. In one embodiment, the method includes the detection of a data synchronization wakeup event while the MPC is operating according to a sleep state. Subsequent to wakeup event, at least one system resource is disabled to provide a minimum number of system resources required to re-establish a network connection. In one embodiment, user data from a network server is synchronized on the MPC without user intervention; the mobile platform system resumes operation according to the sleep state. In one embodiment, a wakeup alarm is programmed according to a user history profile regarding received e-mails. In a further embodiment, data synchronizing involves disabling a display, and throttling the system processor to operate at a reduced frequency. Other embodiments are described and claimed. | 09-16-2010 |
Subhash Joshi, Hillsboro, OR US
| Patent application number | Description | Published |
|---|---|---|
| 20090057842 | SELECTIVE REMOVAL OF ON-DIE REDISTRIBUTION INTERCONNECTS FROM SCRIBE-LINES - Selective removal of on-die redistribution interconnect material from a scribe-line region is generally described. In one example, an apparatus includes a first semiconductor die having a redistribution layer comprising redistribution dielectric and one or more redistribution metal interconnects, a second semiconductor die coupled with the first semiconductor die, the second semiconductor die having a redistribution layer comprising redistribution dielectric and one or more redistribution metal interconnects, and a scribe-line region disposed between the first semiconductor die and second semiconductor die, the scribe-line region having a majority or substantially all of redistribution dielectric or redistribution metal, or suitable combinations thereof, selectively removed to enable die singulation through the scribe-line region. | 03-05-2009 |
Subhash M. Joshi, Beaverton, OR US
| Patent application number | Description | Published |
|---|---|---|
| 20100117229 | Copper-containing C4 ball-limiting metallurgy stack for enhanced reliability of packaged structures and method of making same - The invention relates to a ball-limiting metallurgy stack for an electrical device that contains at least one copper layer disposed upon a Ti adhesion metal layer. The ball-limiting metallurgy stack resists Sn migration toward the upper metallization of the device. | 05-13-2010 |
Subhash M. Joshi, Hillsboro, OR US
| Patent application number | Description | Published |
|---|---|---|
| 20110147855 | DUAL SILICIDE FLOW FOR CMOS - A method for forming a semiconductor device decouples NMOS and PMOS silicide processing and thereby allows independent optimization of at least one characteristic of both NMOS and PMOS devices, and eliminates constraints of using the same silicide process for both NMOS and PMOS, which limits the degree to which the process can be optimized for either technology. | 06-23-2011 |
| 20110156107 | Self-aligned contacts - A transistor comprises a substrate, a pair of spacers on the substrate, a gate dielectric layer on the substrate and between the pair of spacers, a gate electrode layer on the gate dielectric layer and between the pair of spacers, an insulating cap layer on the gate electrode layer and between the pair of spacers, and a pair of diffusion regions adjacent to the pair of spacers. The insulating cap layer forms an etch stop structure that is self aligned to the gate and prevents the contact etch from exposing the gate electrode, thereby preventing a short between the gate and contact. The insulator-cap layer enables self-aligned contacts, allowing initial patterning of wider contacts that are more robust to patterning limitations. | 06-30-2011 |
Varad Joshi, Portland, OR US
| Patent application number | Description | Published |
|---|---|---|
| 20100318954 | MANAGING AND CONTROLLING THE USE OF HARDWARE RESOURCES ON INTEGRATED CIRCUITS - Disclosed herein are representative embodiments of methods and apparatus for managing and allocating hardware resources during RTL synthesis. For example, in one exemplary method disclosed herein, an RTL description of a circuit to be implemented in a target architecture is received. The target architecture of this embodiment comprises a fixed number of hardware resources in a class of hardware resources. One or more operator instances are determined from the RTL description received, where at least some of the operator instances are implementable by the hardware resources in the class of hardware resources. In this embodiment, and prior to initially synthesizing the RTL description into a gate-level netlist, assignment information indicative of how the operator instances are to be implemented using the hardware resources in the class of hardware resources is automatically determined. A graphical user interface is also provided that allows a user to view and modify the assignment information. | 12-16-2010 |