Patent application number | Description | Published |
20090206883 | Thermal Electric NAND Gate - A thermal electric (TE) binary NAND gate logic circuit is provided with a method for NAND logic gating. The method accepts a first input voltage representing an input binary logic state and generates a first thermal electric (TE) temperature in response to the first input voltage. A second input voltage is accepted representing an input binary logic state, and a second TE temperature is generated in response to the second input voltage. In response to the first and second TE temperatures, a NAND logic state output voltage is generated. More explicitly, a first control voltage is generated in response to the first TE temperature, and a second control voltage is generated in response to the second TE temperature. Then, a third TE temperature is generated in response to the first and second control voltages, which in turn generates the output voltage. | 08-20-2009 |
20090206907 | Thermaltronic Analog Device - A method is provided for the electronic processing of analog signals in thermaltronic device. The method accepts an analog input signal, e.g., an AC signal, at a thermaltronic device input and generates a thermal electric (TE) temperature having a first transfer function responsive to the input signal. As opposed to having a digital response, the transfer function is either linear or logarithmic. An analog output signal, e.g., an AC signal, is generated having a second transfer function responsive to the TE, which is likewise either linear or logarithmic. | 08-20-2009 |
20090322343 | 3-D Mapping Focused Beam Failure Analysis - A reflector tool and a method are provided for three-dimensional integrated circuit (IC) failure analysis. An IC (die) has top and bottom surfaces, a perimeter, and a first side. The IC is electrically connected to a current sensing amplifier. The first side of the IC is scanned in the X plane with an infrared laser beam while changes in IC current flow are sensed. The sensed current changes are cross-referenced to the location of the infrared laser beam in the X plane. In one aspect, a plurality of scans are performed on the first side in the X plane, with at a corresponding plurality of steps in the Y plane, so that current changes can be cross-referenced to locations in the X and Y planes. Using this 2-D analysis through the IC side, a human operator or software program can determine defects in the IC. | 12-31-2009 |
20090323287 | Integrated Circuit Cooling Apparatus for Focused Beam Processes - A fixture and method are provided for cooling an IC in the performance of focused beam processes. The method provides a holding/cooling fixture with thermal electric (TE) jaws having an IC interface surface and a heatsink interface. An IC die is secured between the IC interface surfaces of the jaws. Electrical energy is supplied to the TE jaws, creating a negative temperature differential between the IC interface and heatsink interfaces. As a result, the IC die is cooled. A focused beam is applied to a local region of the IC die. Some examples of the focused beam include a focused ion beam (FIB), scanning electron microscope (SEM), E-beam, or a laser scanning microscope (LSM). The focused beam heats the local region of the IC, while the bulk of the IC remains cooled. Typically, each TE jaw includes a plurality of TE elements thermally connected in series. | 12-31-2009 |
20090325322 | Non-Destructive Laser Optical Integrated Circuit Package Marking - A method is provided for laser optically marking integrated circuit (IC) packages in a non-destructive manner. The method provides an IC die encapsulated as a package in a compound of glass spheres and epoxy. An acute angle is defined between a laser optical path and an IC package planar surface. The IC package surface is scanned with a laser, and in response to ablating the IC package surface, a legible mark on the planar surface. | 12-31-2009 |
20100177405 | Optical Fiber Micro Array Lens - An optical fiber micro array lens is provided along with an associated fabrication method. The micro array lens is fabricated from a mesh of optical fibers. The mesh includes a first plurality of cylindrical optical fibers. Each fiber from the first plurality has a flat bottom surface and a hemicylindrical top surface. The top and bottom surfaces are aligned in parallel with a central fiber axis. The mesh also includes a second plurality of cylindrical optical fibers. Each fiber from the second plurality has a hemicylindrical bottom surface overlying and in contact with the top surfaces of the first plurality of optical fibers, and a flat top surface. The top and bottom surfaces are aligned in parallel with a central fiber axis. Each contact of the first and second plurality of optical fibers forms a lens assembly in a micro array of lenses. | 07-15-2010 |
20100259831 | Micro Array Lens Using Optical Fiber - An optical fiber micro array lens is provided along with an associated fabrication method. The micro array lens is fabricated from a mesh of optical fibers. The mesh includes a first plurality of cylindrical optical fibers. Each fiber from the first plurality has a flat bottom surface and a hemicylindrical top surface. The top and bottom surfaces are aligned in parallel with a central fiber axis. The mesh also includes a second plurality of cylindrical optical fibers. Each fiber from the second plurality has a hemicylindrical bottom surface overlying and in contact with the top surfaces of the first plurality of optical fibers, and a flat top surface. The top and bottom surfaces are aligned in parallel with a central fiber axis. Each contact of the first and second plurality of optical fibers forms a lens assembly in a micro array of lenses. | 10-14-2010 |
20100277221 | Method for Solid State Thermal Electric Logic - A method is provided for thermal electric binary logic control. The method accepts an input voltage representing an input logic state. A heat reference is controlled in response to the input voltage. The method supplies an output voltage representing an output logic state, responsive to the heat reference. More explicitly, the heat reference controls the output voltage of a temperature-sensitive voltage divider. For example, the temperature-sensitive voltage divider may be a thermistor voltage divider. | 11-04-2010 |
20100289488 | Optical-Magnetic Kerr Effect Waveform Testing - System and methods are provided for optical-magnetic Kerr effect signal analysis. In one aspect, a test fixture is supplied having parallel conductive lines, with an input of a first line adjacent a resistively loaded output of a second line and a resistively loaded output of the first line adjacent an input of the second line. An optically transparent test region is interposed between the conductive lines, and a metallic reflector underlies the test region. A signal reference is supplied to the input of the first line and a signal under test is supplied to the input of the second line. A light beam having a first angle of polarization is focused through the test region onto the reflector. The intensity of the reflected light is measured and the similarity between the signal under test and the reference signal can be determined in response to the measured light intensity. | 11-18-2010 |
20100327875 | Integrated Circuit Thermally Induced Noise Analysis - A system and method are provided for testing an integrated circuit (IC) using thermally induced noise analysis. The method provides an IC die and supplies electrical power to the IC die. The IC die surface is scanned with a laser, and the laser beam irradiated locations on the IC die surface are tracked. The laser scanning heats active electrical elements underlying the scanned IC die surface. A frequency response of an IC die electrical interface is measured and correlated to irradiated locations. IC die defect regions are determined in response to identifying location-correlated frequency measurements exceeding a noise threshold. For example, a frequency measurement may be correlated to a die surface location, and if frequency measurement exceeds the noise threshold, then circuitry underlying that surface area may be identified as defective. Typically, die defect regions are associated with measurements in the frequency range between about 1 Hertz and 10 kilohertz. | 12-30-2010 |
20110031993 | Curve Tracer Signal Conversion for Integrated Circuit Testing - A curve tracer signal conversion device is provided. The signal conversion device has an input connected to the curve tracer base port to accept a repeating sequence of stepped base signals. The conversion device has a signal input connected to either the curve tracer collector or emitter port, typically the collector. The conversion device has a plurality of signal outputs, where each signal output is sequentially connected to the selected (i.e. collector) curve tracer port in response to a corresponding base step signal. The signals outputs may be provided to a test fixture, for testing a multi-pin integrated circuit (IC). | 02-10-2011 |
20110169478 | Laser Optical Path Detection - A method is provided for detecting laser optical paths in integrated circuit (IC) packages. The method provides an IC die encapsulated as a package in a compound of glass spheres and epoxy. Power is supplied to the IC. The IC is scanned with a laser. Typically, a laser wavelength is used that is minimally absorbed by the glass spheres in the epoxy compound of the IC package, and changes in current to the IC are detected. A detected current change is cross-referenced against a scanned IC package surface region. This process identifies an optical pathway underlying the scanned IC package surface region. In some aspects, this process leads to the identification of a glass sphere-collecting package structure underlying the optical pathway. Examples of a glass sphere-collecting structure might include an inner lead wire, lead frame edge, or die edge. | 07-14-2011 |