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| 20080201597 | WRITE-LEVELING IMPLEMENTATION IN PROGRAMMABLE LOGIC DEVICES - Circuits, methods, and apparatus for memory interfaces that compensate for skew between a clock signal and DQ/DQS signals that may be caused by a fly-by routing topology. The skew is compensated by clocking the DQ/DQS signals with a phase delayed clock signal, where the phase delay has been calibrated. In one example calibration routine, a clock signal is provided to a receiving device. A DQ/DQS signal is also provided and the timing of their reception compared. A delay of the DQ/DQS signal is changed incrementally until the DQ/DQS signal is aligned with the clock signal at the receiving device. This delay is then used during device operation to delay a signal that clocks registers providing the DQ/DQS signals. Each DQ/DQS group can be aligned to the clock, or the DQS and DQ signals in a group may be independently aligned to the clock at the receiving device. | 08-21-2008 |
| 20080291758 | READ-LEVELING IMPLEMENTATIONS FOR DDR3 APPLICATIONS ON AN FPGA - Circuits, methods, and apparatus for transferring data from a device's input clock domain to a core clock domain. One example achieves this by using a retiming element between input and core circuits. The retiming element is calibrated by incrementally sweeping a delay and receiving data at each increment. Minimum and maximum delays where data is received without errors are averaged. This average can then be used to adjust the timing of a circuit element inserted in an input path between an input register clocked by an input strobe signal and an output register clocked by a core clock signal. In one example, an input signal may be delayed by an amount corresponding to the delay setting. In other examples, each input signal is registered using an intermediate register between the input register and the output register, where a clock signal is delayed by an amount corresponding to the delay setting. | 11-27-2008 |
| 20090296503 | READ-LEVELING IMPLEMENTATIONS FOR DDR3 APPLICATIONS ON AN FPGA - Circuits, methods, and apparatus for transferring data from a device's input clock domain to a core clock domain. One example achieves this by using a retiming element between input and core circuits. The retiming element is calibrated by incrementally sweeping a delay and receiving data at each increment. Minimum and maximum delays where data is received without errors are averaged. This average can then be used to adjust the timing of a circuit element inserted in an input path between an input register clocked by an input strobe signal and an output register clocked by a core clock signal. In one example, an input signal may be delayed by an amount corresponding to the delay setting. In other examples, each input signal is registered using an intermediate register between the input register and the output register, where a clock signal is delayed by an amount corresponding to the delay setting. | 12-03-2009 |
| 20110074477 | Techniques for Providing Reduced Duty Cycle Distortion - A feedback loop circuit includes a phase detector and delay circuits. The phase detector generates an output signal based on a delayed periodic signal. The delay circuits are coupled in a delay chain that delays the delayed periodic signal. Each of the delay circuits comprises variable delay blocks and fixed delay blocks that are coupled to form at least two delay paths for an input signal through the delay circuit to generate a delayed output signal. Delays of the variable delay blocks in the delay circuits vary based on the output signal of the phase detector. Each of the delay circuits reroutes the input signal through a different one of the delay paths to generate the delayed output signal based on the output signal of the phase detector during operation of the feedback loop circuit. Each of the variable delay blocks and the fixed delay blocks is inverting. | 03-31-2011 |
| 20110175657 | DUTY CYCLE CORRECTION CIRCUIT FOR MEMORY INTERFACES IN INTEGRATED CIRCUITS - Circuits and a method for correcting duty cycle distortions in an integrated circuit (IC) are disclosed. The IC includes a splitter circuit that is coupled to receive a clock signal. The clock signal is split into two different clock signals. One of the clock signals is an inverted version of the other. A delay circuit is coupled to each of the clock signals. Each of the delay circuits generates a delayed version of the corresponding clock signal. A corrector circuit is coupled to receive both the delayed versions of the clock signals. The corrector circuit generates a clock output signal with a corrected duty cycle. | 07-21-2011 |
| 20110221497 | METHOD AND APPARATUS FOR MINIMIZING SKEW BETWEEN SIGNALS - Delay associated with each of two signals along respective transmission paths is accurately measured using a delay measurement circuit that is fabricated in situ on the actual device where the circuitry for propagating the two signals is fabricated. Thus, the measured delay associated with each of the two signals is subject to the same fabrication-dependent attributes that affect the actual circuitry through which the two signals will be propagated during operation of the device. The skew between the two signals is quantified as the difference in the measured delays. Coarse and fine delay modules are defined within the transmission path of each of the two signals. Based on the measured skew between the two signals, the coarse and fine delay modules are appropriately set to compensate for the skew. The appropriately settings for the coarse and fine delay modules can be stored in non-volatile memory elements. | 09-15-2011 |
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| 20100290180 | USB FLASH DISK WITH NONE-JOINT METALLIC HOUSING - A USB flash disk with a none-joint metallic housing, the main point is that the USB flash disk is formed by inserting an internal structure composed of a printed circuit board, a metallic tray and an insulation upper seat in the metallic housing which is a none-joint rectangular pipe formed by drawing shaping. | 11-18-2010 |
| 20100290181 | USB FLASH DISK - A USB flash disk is disclosed as being inserted therein with an internal structure composed of a printed circuit board, a metallic tray, a lower insulation seat and a clamping strip unit etc. for completing the USB flash disk. | 11-18-2010 |
| 20100321878 | RETRACTABLE USB MEMORY STICK - A retractable USB memory stick includes a metal casing formed of a seamless flat tube having opposing front opening and rear opening, a sliding slot located on one peripheral wall thereof, and first and second locating holes located on the sliding slot, a PC board having a front USB interface circuit and a rear memory IC package, and an insulation PC board holder holding the PC board and slidably mounted in the metal casing. The insulation PC board holder has a spring strip bridged on the outside wall thereof, a sliding block located on the spring strip and forced by the spring power of the spring strip into the sliding slot of the metal casing, and a retaining block protruded from the sliding block for selectively engaging the first locating hole or second locating hole of the metal casing to lock the insulation PC board holder to the metal casing in the extended position and received position. | 12-23-2010 |
| 20110011146 | METHOD OF FORMING A TENON ON ONE SIDE OF A METAL PLATE MEMBER - A method of forming a tenon on one side of a metal plate member by means of punching the wall of one side of the metal plate member with a punch or punches to form a protrusion and then punching the protrusion with a punch rod to extend the height of the protrusion and to deform the protrusion into a tubular configuration. | 01-20-2011 |
| 20110013354 | MEMORY STICK - A memory stick includes a | 01-20-2011 |
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| 20100045349 | PROGRAMMABLE HIGH-SPEED INTERFACE - Methods and apparatus for providing either high-speed, or lower-speed, flexible inputs and outputs. An input and output structure having a high-speed input, a high-speed output, a low or moderate speed input, and an low or moderate speed output is provided. One of the input and output circuits are selected and the others are deselected. The high-speed input and output circuits are comparatively simple, in one example having only a clear signal for a control line input, and are able to interface to lower speed circuitry inside the core of an integrated circuit. The low or moderate speed input and output circuits are more flexible, for example, having preset, enable, and clear as control line inputs, and are able to support JTAG boundary testing. These parallel high and lower speed circuits are user selectable such that the input output structure is optimized between speed and functionality depending on the requirements of the application. | 02-25-2010 |
| 20110227606 | PROGRAMMABLE HIGH-SPEED INTERFACE - Methods and apparatus for providing either high-speed, or lower-speed, flexible inputs and outputs. An input and output structure having a high-speed input, a high-speed output, a low or moderate speed input, and an low or moderate speed output is provided. One of the input and output circuits are selected and the others are deselected. The high-speed input and output circuits are comparatively simple, in one example having only a clear signal for a control line input, and are able to interface to lower speed circuitry inside the core of an integrated circuit. The low or moderate speed input and output circuits are more flexible, for example, having preset, enable, and clear as control line inputs, and are able to support JTAG boundary testing. These parallel high and lower speed circuits are user selectable such that the input output structure is optimized between speed and functionality depending on the requirements of the application. | 09-22-2011 |
