| Patent application number | Description | Published |
|---|
| 20080225587 | Integrated Circuits, Methods for Manufacturing Integrated Circuits, Integrated Memory Arrays - The present invention relates generally to integrated circuits, to methods for manufacturing integrated circuits, and to integrated memory arrays. | 09-18-2008 |
| 20080237694 | Integrated circuit, cell, cell arrangement, method for manufacturing an integrated circuit, method for manufacturing a cell, memory module - The invention relates to integrated circuits, to a cell, to a cell arrangement, to a method for manufacturing an integrated circuit, to a method for manufacturing a cell, and to a memory module. In an embodiment of the invention, an integrated circuit is provided having a cell, the cell including a low-k dielectric layer, a first high-k dielectric layer disposed above the low-k dielectric layer, a charge trapping layer disposed above the first high-k dielectric layer, and a second high-k dielectric layer disposed above the charge trapping layer. | 10-02-2008 |
| 20090026524 | Stacked Circuits - An integrated circuit includes a first integrated circuit layer including at least one first transistor channel region and having a wafer bonding interface. The integrated circuit may further include at least one second integrated circuit layer including at least one second transistor channel region and being arranged at the wafer bonding interface of the first integrated circuit layer. | 01-29-2009 |
| 20090029512 | SEMICONDUCTOR MEMORY HAVING CHARGE TRAPPING MEMORY CELLS AND FABRICATION METHOD THEREOF - A semiconductor memory having charge trapping memory cells and fabrication method thereof. The direction of current flow of each channel region of the memory transistors runs transversely with respect to the relevant word line, the bit lines are arranged on the top side of the word lines and in a manner electrically insulated from the latter, and electrically conductive local interconnects of source-drain regions are present, which are arranged in sections in interspaces between the word lines and in a manner electrically insulated from the latter and connected to the bit lines, wherein gate electrodes are arranged in trenches at least partly formed in the memory substrate. | 01-29-2009 |
| 20090039329 | Integrated Circuit Having a Cell with a Resistivity Changing Layer - In an embodiment of the invention, an integrated circuit having a cell is provided. The cell may include a field effect transistor structure which includes a gate stack and a resistivity changing material structure disposed above the gate stack, wherein the resistivity changing material structure includes a resistivity changing material which is configured to change its resistivity in response to the application of an electrical voltage to the resistivity changing material structure. | 02-12-2009 |
| 20090059673 | Method of Operating an Integrated Circuit for Reading the Logical State of a Memory Cell - In an embodiment of the invention, a method of operating an integrated circuit for reading the logical state of a selected one of a plurality of memory cells included within a memory cell string in the integrated circuit is provided. | 03-05-2009 |
| 20090072274 | INTEGRATED CIRCUIT INCLUDING A FIRST GATE STACK AND A SECOND GATE STACK AND A METHOD OF MANUFACTURING - An integrated circuit including a first gate stack and a second gate stack and a method of manufacturing is disclosed. One embodiment provides non-volatile memory cells including a first gate stack and a gate dielectric on a first surface section of a main surface of a semiconductor substrate, and a second gate stack including a memory layer stack on a second surface section. A first pattern is transferred into the first gate stack and a second pattern into the second gate stack. | 03-19-2009 |
| 20090097317 | Integrated Circuit Having NAND Memory Cell Strings - Embodiments of the present invention relate generally to integrated circuits and methods for manufacturing an integrated circuit. In an embodiment of the invention, an integrated circuit having a memory cell is provided. The memory cell may include a trench in a carrier, a charge trapping layer structure in the trench, the charge trapping layer structure comprising at least two separate charge trapping regions, electrically conductive material at least partially filled in the trench, and source/drain regions next to the trench. | 04-16-2009 |
| 20090200533 | Resistive Memory Element and Method of Fabrication - An integrated circuit including a memory cell and a method of manufacturing the integrated circuit are described. The memory cell includes a buried gate select transistor and a resistive memory element coupled to the buried gate select transistor. The resistive memory element stores information based on a resistivity of the resistive memory element. | 08-13-2009 |
| 20090201740 | INTEGRATED CIRCUIT, METHOD TO PROGRAM A MEMORY CELL ARRAY OF AN INTEGRATED CIRCUIT, AND MEMORY MODULE - An integrated circuit having a memory cell arrangement with a plurality of memory cells and a memory cell arrangement controller is provided. The memory cell arrangement controller is configured such that during programming of at least one memory cell of the plurality of memory cells, at least one memory cell, which is arranged adjacent to the memory cell to be programmed, is driven to shield the memory cell to be programmed. | 08-13-2009 |
| 20090244949 | Memory Device and Method Providing Logic Connections for Data Transfer - In an embodiment, a method for transferring data in a memory device is provided. The method may include transferring data from a first memory cell arrangement including a plurality of memory cells to a second memory cell arrangement including a plurality of memory cells via a connecting circuit arrangement coupled to the plurality of memory cell arrangements and providing a plurality of controllable connections via a plurality of connecting circuit terminals, the memory cell arrangements being connected with at least one connecting circuit terminal of the plurality of connecting circuit terminals, wherein the connecting circuit is configured to provide arbitrarily controllable signal flow connections between the plurality of connecting circuit terminals. The data are transferred via a logic connection using the controllable connections. Simultaneously, a further logic connection may be provided to a memory cell arrangement of the memory cell arrangements using the controllable connections. | 10-01-2009 |
| 20090251968 | Integrated circuit having a base structure and a nanostructure - In an embodiment, an integrated circuit may include a metallically conductive structure, a base structure having a crystal orientation, the base structure being adjacent to the metallically conductive structure, and a nanostructure disposed on the base structure, the nanostructure having substantially the same crystal orientation as the base structure. | 10-08-2009 |
| 20090261397 | Integrated Circuit with Floating-Gate Electrodes Including a Transition Metal and Corresponding Manufacturing Method - An integrated circuit is described. The integrated circuit may comprise a multitude of floating-gate electrodes, wherein at least one of the floating-gate electrodes has a lower width and an upper width, the lower width being larger than the upper width, and wherein the at least one of the floating-gate electrodes comprises a transition metal. A corresponding manufacturing method for an integrated circuit is also described. | 10-22-2009 |
| 20090272958 | Resistive Memory - An integrated circuit including a memory cell and method of manufacturing the integrated circuit are described. The memory cell includes a diode and a resistive memory element coupled to the diode. The resistive memory element includes a thin oxide storage layer that uses multiple resistance levels to store more than one bit of information in the resistive memory element. | 11-05-2009 |
| 20100019345 | Integrated Circuit with an Active Area Line Having at Least One Form-Supporting Element and Corresponding Method of Making an Integrated Circuit - An integrated circuit is described. The integrated circuit may have: an active area line formed of a material of a semiconductor substrate with a first longitudinal direction parallel to an upper surface of the semiconductor substrate; wherein the active area line has at least one form-supporting element extending in a second longitudinal direction parallel to the upper surface of the semiconductor substrate; and wherein the second longitudinal direction is arranged with regard to the first longitudinal direction in an angle unequal to 0 degree and unequal to 180 degree. | 01-28-2010 |
