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Jose De Jesus Pineda De Gyvez, Eindhoven NL

Jose De Jesus Pineda De Gyvez, Eindhoven NL

Patent application numberDescriptionPublished
20090134904ANALOG IC HAVING TEST ARRANGEMENT AND TEST METHOD FOR SUCH AN IC - An integrated circuit (IC) comprises a plurality of analog stages (05-28-2009
20100013493TEST PREPARED INTEGRATED CIRCUIT WITH AN INTERNAL POWER SUPPLY DOMAIN - The integrated circuit (01-21-2010
20100049465TESTABLE ELECTRONIC DEVICE FOR WIRELESS COMMUNICATION - An electronic device is disclosed comprising a transceiver stage (02-25-2010
20100109676ANALOG CIRCUIT TESTING AND TEST PATTERN GENERATION - Test vectors for structural testing of an analog circuit are selected by first selecting an initial set of test input vectors for the analog circuit. A set of faults is selected, comprising faults that each correspond to a respective node in the analog circuit and corresponding fault voltage value for that node. A measure of overlap is computed between probability distributions of test output signal values for the analog circuit in response to the test input vectors in the presence and absence of each of the faults from said set of faults respectively, as a function of estimated statistical spread of component and/or process parameter values in the analog circuit. Test input vectors are selected from the initial set of test input vectors for use in testing on the basis of whether the measure of overlap for at least one if the faults is below a threshold value in response to the selected test input vector under control of the test selection computer.05-06-2010
20100202192STATIC MEMORY DEVICES - A semiconductor memory device includes n-wells (08-12-2010
20100231252TESTABLE INTEGRATED CIRCUIT AND IC TEST METHOD - An integrated circuit (09-16-2010
20100281245METHOD AND APPARATUS FOR TUNING A DIGITAL SYSTEM - A digital system 11-04-2010
20110083116POWER SWITCH DESIGN METHOD AND PROGRAM - A method of designing a power switch block (04-07-2011
20110095803Adaptive control of power supply for integrated circuits - The present invention relates to a circuit arrangement and method for controlling power supply in an integrated circuit wherein at least one working parameter of at least one electrically isolated circuit region (04-28-2011

Patent applications by Jose De Jesus Pineda De Gyvez, Eindhoven NL