Joong-Hyun

Joong-Hyun Park, Suwon-Si KR

Patent application number	Description	Published
20110067759	SOLAR CELL AND MANUFACTURING METHOD THEREOF - A solar cell includes; a substrate; a first electrode disposed on the substrate, and including a first groove formed therein, a semiconductor layer disposed on the first electrode, and including a second groove formed therein, and a second electrode disposed on the semiconductor layer and connected to the first electrode via the second groove, wherein a third groove passing through the first electrode, the semiconductor layer, and the second electrode is formed in a first region, a fourth groove passing through only the semiconductor layer and the second electrode is formed in a second region, and the first region and the second region are alternately disposed along a direction of extension of the third groove.	03-24-2011

Patent application number	Description	Published
20100193006	SOLAR CELL MODULE AND METHOD OF MANUFACTURING THE SAME - A solar cell module includes a substrate, a lower electrode layer, a semiconductor layer and an upper electrode layer for an embodiment. The lower electrode layer may include a plurality of area-separating grooves separating the substrate into an active area and a peripheral area surrounding the active area, and a plurality of first cell-separating grooves formed in the active area. The semiconductor layer is formed on the lower electrode layer. The semiconductor layer includes a plurality of second cell-separating grooves that are spaced apart from the first cell-separating grooves. The upper electrode layer is formed on the semiconductor layer. The upper electrode layer includes a plurality of third cell-separating grooves that are spaced apart from the second separating grooves.	08-05-2010

Patent application number	Description	Published
20080197413	THIN FILM TRANSISTOR AND METHOD OF MANUFACTURING THE SAME - Provided are a thin film transistor and a method of manufacturing the same. The thin film transistor includes: a lower structure; a semiconductor layer formed on the lower structure and including a plurality of doping regions; a first insulating layer and a second insulating layer formed on the semiconductor layer and separated from each other; a third insulating layer formed on the first insulating layer and the second insulating layer; and a gate electrode layer formed between regions of the third insulating layer respectively corresponding to the first insulating layer and the second insulating layer.	08-21-2008