Patent application number | Description | Published |
20150195766 | METHOD AND USER TERMINAL FOR DYNAMICALLY CONTROLLING ROUTING - A method and user terminal for dynamically controlling routing are provided. The method may provide an effective routing mechanism in a system to which a plurality of radio access technologies (RATs) are applied. The method may perform routing based on characteristics of the RATs, a degree of a generated traffic load, a user preference of a RAT, and the like. | 07-09-2015 |
20150201414 | METHOD OF ALLOCATING SLOT AND ACCESSING CHANNEL IN WIRELESS LOCAL AREA NETWORK (WLAN) - A method of assigning a slot and accessing a channel in a wireless local area network (WLAN) is provided. A station may attempt to access a channel based on a plurality of candidate slots assigned to the station. | 07-16-2015 |
20150282193 | METHOD AND APPARATUS FOR AVOIDING COMMUNICATION INTERFERENCE IN WIRELESS COMMUNICATION SYSTEM - Provided is a communication control apparatus for controlling data transmission performed by a first communication module and a second communication module, each using a different communication scheme, the apparatus including a storing unit to store, in a data structure, channel information on a communication module for avoiding communication interference between the first communication module and the second communication module, and a processor to set, based on the channel information, a channel different from a channel used by the first communication module as a channel of the second communication module, wherein the first communication module and the second communication module are included in an identical device. | 10-01-2015 |
Patent application number | Description | Published |
20100163896 | Nitride Red Phosphors and White Light Emitting Diode Using Rare-Earth-Co-Doped Nitride Red Phosphors - Disclosed are nitride red phosphors and white light emitting diodes using the same. More particularly, the present invention provides a nitride red phosphor with easily controlled composition of phosphor fraction and improved uniformity and color gamut thereof, a method for preparation thereof, a white light emitting diode with excellent color rendition and high light emitting efficiency, and a white light emitting diode package using the same. | 07-01-2010 |
20110034581 | Transparent Siloxane Resin Composition for Optical Applications - Provided is a transparent siloxane resin composition for optical applications, including: (1) a vinyl-oligosiloxane hybrid; (2) an organohydrosilicon compound having two or more silicon-bonded hydrogen atoms; and (3) a metal catalyst. | 02-10-2011 |
20120009120 | THERMAL CRACKING RESISTANT ZEOLITE MEMBRANE AND METHOD OF FABRICATING THE SAME - The present disclosure relates to a thermal cracking resistant zeolite membrane and a method of fabricating the same. The method includes dissolving an alumina-based material, a silica-based material and sodium hydroxide in water to prepare an aqueous solution, stirring the aqueous solution to form a hydrothermal solution, preparing a slurry of zeolite seeds through wet-type vibration pulverization and centrifugal separation of zeolite powder, passing the zeolite seeds through a support by vacuum filtration such that the zeolite seeds can be infiltrated into an inner region of the support ranging from a depth of 3 μm to a depth corresponding to 50% of a total thickness of the support, and immersing the support into the hydrothermal solution for hydrothermal treatment to grow a dense zeolite separation layer not only on the surface of the support but also on the inner region thereof. The zeolite membrane prevents the occurrence of thermal cracking on the zeolite separation layer, thereby providing good thermal stability and separation performance during heating and at a target processing temperature. | 01-12-2012 |
20120292825 | APPARATUS FOR MANUFACTURING SILICON SUBSTRATE FOR SOLAR CELL USING CONTINUOUS CASTING FACILITATING TEMPERATURE CONTROL AND METHOD OF MANUFACTURING SILICON SUBSTRATE USING THE SAME - The present disclosure provides an apparatus for manufacturing a silicon substrate for solar cells using continuous casting, which can improve quality, productivity and energy conversion efficiency of the silicon substrate. The apparatus includes a crucible unit configured to receive raw silicon and having a discharge port, a heating unit provided to an outer wall and an external bottom surface of the crucible unit and heating the crucible unit to form molten silicon, a casting unit casting the molten silicon into a silicon substrate, a cooling unit rapidly cooling the silicon substrate, and a transfer unit disposed at one end of the cooling unit and transferring the silicon substrate. The casting unit includes a casting unit body having a casting space defined therein to be horizontally connected to the discharge port, and an assistant heating mechanism that preheats the casting unit body to control a solidification temperature of the silicon substrate. | 11-22-2012 |
20120328498 | METHOD FOR PREPARING HIGH-PURITY LITHIUM CARBONATE FROM BRINE - The present disclosure provides a method of preparing highly pure lithium carbonate from brine. The method includes adding an adsorbent to the brine, from which the magnesium ions Mg | 12-27-2012 |
20130001168 | APPARATUS AND METHOD FOR ADSORBING AND DESORBING LITHIUM IONS USING A CCD PROCESS - The present disclosure provides a method for adsorption/desorption of lithium ions from brine, which employs a counter current decantation process in adsorption/desorption of lithium ions, thereby achieving an adsorption rate of 65±5% and a desorption rate of 95±3%. The method includes supplying brine into one of a plurality of adsorption reactors, adsorbing lithium ions to an adsorbent by supplying the adsorbent to the adsorption reactor to which the brine is supplied and forcing the brine and the adsorbent to sequentially flow backwards inside the respective adsorption reactors, and desorbing the lithium ions from the brine by forcing the adsorbent to which the lithium ions are adsorbed to sequentially flow backwards inside a plurality of desorption reactors. Here, the brine and the adsorbent are stirred by a stirrer to maintain the adsorbent in an intermediate state instead of settling or floating inside the respective adsorption reactors. | 01-03-2013 |
20130067959 | A GRAPHITE CRUCIBLE FOR SILICON ELECTROMAGNETIC INDUCTION HEATING AND APPARATUS FOR SILICON MELTING AND REFINING USING THE GRAPHITE CRUCIBLE - The present disclosure provides a graphite crucible induction-based silicon melting. The graphite crucible comprises a cylindrical body having a plurality of slits which is formed through an outer wall and an inner wall of the cylindrical body and a bottom part connected with an edge of the cylindrical body to seal an end of the cylindrical body. | 03-21-2013 |
20130263777 | APPARATUS FOR MANUFACTURING SILICON SUBSTRATE - There is disclosed an apparatus for manufacturing a silicon substrate including a crucible part, a molding part extended from an outlet of the crucible part, the molding part comprising a molding space where a silicon substrate is formed, and a dummy bar inserted in the molding space from a predetermined portion of the molding part, wherein the dummy bar is formed of a single-crystalline material. | 10-10-2013 |
20130291595 | APPARATUS FOR MANUFACTURING HIGH PURITY POLYSILICON USING ELECTRON-BEAM MELTING AND METHOD OF MANUFACTURING HIGH PURITY POLYSILICON USING THE SAME - Apparatus and method for manufacturing high purity polysilicon. The apparatus includes a vacuum chamber maintaining a vacuum atmosphere; first and second electron guns disposed at an upper side of the vacuum chamber to irradiate electron beams into the vacuum chamber; a silicon melting unit placed on a first electron beam-irradiating region corresponding to the first electron gun and in which powdery raw silicon is placed and melted by the first electron beam; and a unidirectional solidification unit placed on a second electron beam-irradiating region corresponding to the second electron gun and connected to the silicon melting unit via a runner. The unidirectional solidification unit is formed at a lower part thereof with a cooling channel and is provided therein with a start block driven in a downward direction. | 11-07-2013 |
20130291596 | APPARATUS FOR MANUFACTURING POLYSILICON BASED ELECTRON-BEAM MELTING USING DUMMY BAR AND METHOD OF MANUFACTURING POLYSILICON USING THE SAME - Methods and apparatus for manufacturing high purity polysilicon. The apparatus includes a vacuum chamber; first and second electron guns disposed at an upper side of the vacuum chamber to irradiate electron beams into the vacuum chamber; a silicon melting unit which is placed on a first electron beam-irradiating region corresponding to the first electron gun and to which powdery raw silicon is fed and melted by the first electron beam; and a unidirectional solidification unit placed on a second electron beam-irradiating region corresponding to the second electron gun. The unidirectional solidification unit is provided therein with a start block driven in a downward direction to transfer molten silicon in the downward direction and is formed at a lower side thereof with a cooling channel. The start block includes a dummy bar having a silicon button joined to an upper portion of the dummy bar. | 11-07-2013 |
20140301910 | APPARATUS FOR PREPARING SILICON NANOPARTICLE USING ICP - Disclosed is an apparatus for preparing silicon nanoparticles. The apparatus includes a corona discharge section charging silicon nanoparticles to exhibit unipolarity in order to prevent agglomeration of the silicon nanoparticles after the silicon nanoparticles are generated from an injected gas by plasma reaction of an inductively coupled plasma (ICP) coil. The apparatus may facilitate grain size control of silicon nanoparticles while improving discharge performance of a mesh filter for collection of generated nanoparticles by preventing agglomeration of the silicon nanoparticles generated by plasma reaction using inductively coupled plasma (ICP), and may permit replacement of the mesh filter even during operation of the apparatus, thereby improving productivity while reducing manufacturing costs. | 10-09-2014 |
20150090406 | METHOD FOR DISASSEMBLING PHOTOVOLTAIC MODULE - Provided is a method of disassembling a photovoltaic module. The method includes: applying heat to the photovoltaic module in an oxidizing atmosphere; removing an insulating protective layer wrapping a photovoltaic cell of the photovoltaic module; and obtaining the photovoltaic cell of the photovoltaic module. | 04-02-2015 |
20150203938 | METHOD FOR LEACHING VALUABLE METALS CONTAINED IN WASTE DENITRIFICATION CATALYST BY USING ROASTING AND WATER LEACHING - Disclosed is a method for effectively leaching valuable metals such as vanadium and tungsten contained in a waste denitrification catalyst by using roasting and water leaching. According to the present invention, the method for leaching valuable metals contained in a waste denitrification catalyst comprises the steps of: (a) mixing a waste denitrification catalyst containing vanadium (V) and tungsten (W) in the form of an oxide with an alkali metal compound to form a mixture; (b) roasting the mixture to generate a roasting product comprising sodium vanadate (NaVO | 07-23-2015 |
20160002055 | SiOx NANOPARTICLE MANUFACTURING APPARATUS INCLUDING CRUCIBLE FOR SILICON MELTING HAVING SLIDING TYPE TAPPING STRUCTURE AND MANUFACTURING METHOD OF SiOx NANOPARTICLE USING THE SAME - Disclosed herein are a SiOx nanoparticle manufacturing apparatus that can not only manufacture a SiOx nanoparticle in large quantities but also prevent a silicon melt residue from being stuck and solidified on an inner bottom surface of a crucible by designing a sliding type tapping structure, and a SiOx nanoparticle manufacturing method using the same. | 01-07-2016 |
Patent application number | Description | Published |
20090117497 | METHOD OF FORMING PATTERN USING FINE PITCH HARD MASK - A method of forming a fine pattern of a semiconductor device using a fine pitch hard mask is provided. A first hard mask pattern including first line patterns formed on an etch target layer of a substrate with a first pitch is formed. A first layer including a top surface where a recess is formed between adjacent first line patterns is formed. A second hard mask pattern including second line patterns within the recess is formed. An anisotropic etching process is performed on the first layer using the first and the second line patterns as an etch mask. Another anisotropic etching process is performed on the etch target layer using the first and the second hard mask patterns as an etch mask. | 05-07-2009 |
20100197139 | METHOD OF FORMING A HARD MASK AND METHOD OF FORMING A FINE PATTERN OF SEMICONDUCTOR DEVICE USING THE SAME - A method of forming hard mask employs a double patterning technique. A first hard mask layer is formed on a substrate, and a first sacrificial pattern is formed on the first hard mask layer by photolithography. Features of the first sacrificial pattern are spaced from one another by a first pitch. A second hard mask layer is then formed conformally on the first sacrificial pattern and the first hard mask layer so as to delimit recesses between adjacent features of the first sacrificial pattern. Upper portions of the second hard mask layer are removed to expose the first sacrificial pattern, and the exposed first sacrificial pattern and the second sacrificial pattern are removed. The second hard mask layer and the first hard mask layer are then etched to form a hard mask composed of residual portions of the first hard mask layer and the second hard mask layer. A fine pattern of a semiconductor device, such as a trench isolation region or a pattern of contact holes, can be formed using the hard mask as an etch mask. | 08-05-2010 |
20100203705 | SEMICONDUCTOR DEVICE WITH IMPROVED OVERLAY MARGIN AND METHOD OF MANUFACTURING THE SAME - Semiconductor devices with an improved overlay margin and methods of manufacturing the same are provided. In one aspect, a method includes forming a buried bit line in a substrate; forming an isolation layer in the substrate to define an active region, the isolation layer being parallel to the bit line without overlapping the bit line; and forming a gate line including a gate pattern and a conductive line by forming the gate pattern in the active region and forming a conductive line that extends at a right angle to the bit line across the active region and is electrically connected to the gate pattern disposed thereunder. The gate pattern and the conductive line can be integrally formed. | 08-12-2010 |
20110269294 | METHOD OF FORMING A HARD MASK AND METHOD OF FORMING A FINE PATTERN OF SEMICONDUCTOR DEVICE USING THE SAME - A method of forming hard mask employs a double patterning technique. A first hard mask layer is formed on a substrate, and a first sacrificial pattern is formed on the first hard mask layer by photolithography. Features of the first sacrificial pattern are spaced from one another by a first pitch. A second hard mask layer is then formed conformally on the first sacrificial pattern and the first hard mask layer so as to delimit recesses between adjacent features of the first sacrificial pattern. Upper portions of the second hard mask layer are removed to expose the first sacrificial pattern, and the exposed first sacrificial pattern and the second sacrificial pattern are removed. The second hard mask layer and the first hard mask layer are then etched to form a hard mask composed of residual portions of the first hard mask layer and the second hard mask layer. A fine pattern of a semiconductor device, such as a trench isolation region or a pattern of contact holes, can be formed using the hard mask as an etch mask. | 11-03-2011 |
20130260559 | METHODS FOR FORMING FINE PATTERNS OF A SEMICONDUCTOR DEVICE - Methods of forming fine patterns are provided. The methods may include forming first hard mask patterns extending in a first direction on a lower layer, forming second hard mask patterns filling gap regions between the first hard mask patterns, forming first mask patterns extending in a second direction perpendicular to the first direction on the first and second hard mask patterns, etching the first hard mask patterns using the first mask patterns as etch masks to form first openings, forming second mask patterns filling the first openings and extending in the second direction, and etching the second hard mask patterns using the second mask patterns as etch masks to form second openings spaced apart from the first openings in a diagonal direction with respect to the first direction. | 10-03-2013 |
20130260562 | METHODS FOR FORMING FINE PATTERNS OF A SEMICONDUCTOR DEVICE - A method may include forming first hard mask patterns and second hard mask patterns extending in a first direction and repeatedly and alternately arranged on a lower layer, forming third mask patterns extending in a second direction perpendicular to the first direction on the first and second hard mask patterns, etching the first hard mask patterns using the third mask patterns to form first openings, forming filling patterns filling the first openings and gap regions between the third mask patterns, forming spacers on both sidewalls of each of the filling patterns, after removing the third mask patterns, and etching the second hard mask patterns using the filling patterns and the spacers to form second openings. | 10-03-2013 |
20150309411 | Methods of Forming Pattern by Using Dual Tone Development Processes - Methods of forming a pattern are provided. The methods may include forming a dual tone photoresist layer on a support layer, forming a low light exposure region, a middle light exposure region, and a high light exposure region in a first region of the dual tone photoresist layer and forming a low light exposure region and a middle light exposure region in a second region of the dual tone photoresist layer by exposing the dual tone photoresist layer to light by using a mask comprising a gray feature. The method may also include forming preliminary patterns in the first region by performing a positive development process and forming first patterns which are spaced apart from one another in the first region and second patterns which are spaced apart from one another in the second region by performing a negative development process. | 10-29-2015 |