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Joon-Hee
Joon-Hee Cho, Daejeon KR
| Patent application number | Description | Published |
|---|---|---|
| 20120123078 | METALLOCENE COMPOUND, CATALYST COMPOSITION COMPRISING THE SAME, AND AN OLEFINIC POLYMER PRODUCED USING THE SAME - The present invention relates to a novel metallocene compound, a catalyst composition comprising the same, and to olefinic polymers produced using the same. The metallocene compound according to the present invention and the catalyst composition comprising the same can be used when producing olefinic polymers, have outstanding copolymerisation properties, and can produce olefinic polymers of high molecular weight. In particular, when the metallocene compound according to the present invention is employed, highly heat resistant block copolymers can be produced, and olefinic polymers can be produced which have a high melting point (Tm) even if the comonomer content is increased when producing the olefinic polymer. | 05-17-2012 |
Joon-Hee Jeong, Sugi-Gu KR
| Patent application number | Description | Published |
|---|---|---|
| 20100143235 | Method of manufacturing carbon nanofiber and apparatus for manufacturing the same - The present invention provides a method of manufacturing a carbon nanofiber of the present invention including dissolving a catalyst-precursor and a supporter-precursor into a solvent of a hydrocarbon-based compound to prepare a reacting solution, atomizing the reacting solution, thermally decomposing the atomized reacting solution to forming particles of the carbon nanofiber, and collecting the particles of the carbon nanofiber. In accordance with the above method, the carbon nanofiber is efficiently mass-produced in situ process and in batch process. | 06-10-2010 |
Joon-Hee Kim, Seongnam-Si KR
| Patent application number | Description | Published |
|---|---|---|
| 20100173211 | FUEL CELL SYSTEM AND FUEL CELL POWER MANAGING METHOD - A fuel cell system and a fuel cell power managing method in which the fuel cell system controls a current output of a fuel cell by adjusting a target voltage value of the fuel cell according to a difference between a current value of the fuel cell and a target constant current value. By doing so, the fuel cell system may allow the fuel cell to stably and constantly output a constant current. | 07-08-2010 |
Joon-Hee Lee, Goyang-Si KR
| Patent application number | Description | Published |
|---|---|---|
| 20120086506 | APPARATUS FOR COMPENSATING FOR PROCESS VARIATION OF RESISTOR IN ELECTRONIC CIRCUIT - An electronic circuit apparatus for compensating for a process variation of a resistor in an electronic circuit is provided. The electronic circuit includes a detecting part for generating a tune voltage corresponding to a process variation value of the at least one resistor, and a compensating part for compensating for a process variation of the at least one resistor using the tune voltage. | 04-12-2012 |
Joon-Hee Lee, Gyeonggi-Do KR
| Patent application number | Description | Published |
|---|---|---|
| 20080237679 | SEMICONDUCTOR DEVICES WITH SIDEWALL CONDUCTIVE PATTERNS AND METHODS OF FABRICATING THE SAME - A gate pattern is disclosed that includes a semiconductor substrate, a lower conductive pattern, an upper conductive pattern and a sidewall conductive patter. The lower conductive pattern is on the substrate. The insulating pattern is on the lower conductive pattern. The upper conductive pattern is on the insulating pattern opposite to the lower conductive pattern. The sidewall conductive pattern is on at least a portion of sidewalls of the upper conductive pattern and the lower conductive pattern. The sidewall conductive pattern electrically connects the upper conductive pattern and the lower conductive pattern. An upper edge portion of the lower conductive pattern may be recessed relative to a lower edge portion of the lower conductive pattern to define a ledge thereon. The sidewall conductive pattern may be directly on the ledge and sidewall of the recessed upper edge portion of the lower conductive pattern. | 10-02-2008 |
| 20080268218 | INSULATED ELECTRIC WIRE - The present invention relates to an insulated electric wire. The insulated electric wire according to the present invention includes a high adhesion resin layer made of a polyamideimide resin containing a compound having a polar group in a molecular structure of an insulation material; and a high flexibility resin layer provided on the high adhesion resin layer. The present invention advantageously improves adherence between a polyamideimide resin and a conductor, and provides adhesive strength with the conductor to improve flexibility of the insulated electric wire and at the same time to improve flexibility of an insulator without deterioration of heat resistance of the insulator. | 10-30-2008 |
| 20090202830 | ENAMEL VARNISH COMPOSITION FOR ENAMEL WIRE AND ENAMEL WIRE USING SAME - Disclosed are enamel varnish compositions for an enamel wire and an enamel wire using the same. The present invention relates to enamel varnish compositions for an enamel wire in which a polymeric resin component is included in an organic solvent, wherein the polymeric resin component includes a first polyamideimide resin; and a second resin having polyamideimide in which a triazine ring is introduced into a major chain. The enamel wire, in which such a coating pigment composition is applied to the innermost layer, has the increased adhesivity of the insulated coating layer to the conducting wire, as well as the excellent physical properties such as the wear resistance and flexibility, etc. | 08-13-2009 |
| 20110217835 | METHODS OF FABRICATING SEMICONDUCTOR DEVICES WITH SIDEWALL CONDUCTIVE PATTERNS - A gate pattern is disclosed that includes a semiconductor substrate, a lower conductive pattern, an upper conductive pattern, and a sidewall conductive pattern. The lower conductive pattern is on the substrate. The insulating pattern is on the lower conductive pattern. The upper conductive pattern is on the insulating pattern opposite to the lower conductive pattern. The sidewall conductive pattern is on at least a portion of sidewalls of the upper conductive pattern and the lower conductive pattern. The sidewall conductive pattern electrically connects the upper conductive pattern and the lower conductive pattern. An upper edge portion of the lower conductive pattern may be recessed relative to a lower edge portion of the lower conductive pattern to define a ledge thereon. The sidewall conductive pattern may be directly on the ledge and sidewall of the recessed upper edge portion of the lower conductive pattern. | 09-08-2011 |
Joon-Hee Lee, Seongnam-Si KR
| Patent application number | Description | Published |
|---|---|---|
| 20090072322 | SEMICONDUCTOR DEVICES INCLUDING LINE PATTERNS SEPARATED BY CUTTING REGIONS - Semiconductor devices are provided. A semiconductor device can include a substrate and a plurality of dummy line patterns on the substrate that extend in a first direction parallel with one another. Each of the dummy line patterns can include a plurality of sub-line patterns aligned along the first direction and which are separated from each other by at least one cutting region therebetween. The dummy line patterns can include first and second dummy line patterns which are adjacent to each other in a second direction that is perpendicular to the first direction. At least one of the cutting regions between a pair of sub-line patterns of the first dummy line pattern is aligned with and bounded by one of the sub-line patterns of the second dummy line pattern in the second direction. | 03-19-2009 |
| 20100207690 | METHOD OF APPLYING WIRE VOLTAGE TO SEMICONDUCTOR DEVICE - A method of applying a wire voltage to a semiconductor device including a plurality of active regions and a field region insulating the plurality of active regions, wherein the field region includes a plurality of wires. The method includes applying an operating voltage required for an operation of the semiconductor device to at least one of the plurality of wires, and applying a voltage lower than the operating voltage to a wire adjacent to at least one of the plurality of active regions from among the plurality of wires. Thus, leakage current caused by an imaginary parasitic transistor due to a wire of the field region may be prevented. | 08-19-2010 |
Joon-Hee Lee, Yongin-Si KR
| Patent application number | Description | Published |
|---|---|---|
| 20090037784 | Semiconductor memory device having mount test circuits and mount test method thereof - A semiconductor memory device having a mount test circuit and a mount test method thereof are provided. The test circuit for use in a semiconductor memory device including a plurality of memory blocks may include a comparison unit for comparing test data of at least two memory blocks selected from the plurality of memory blocks, deciding whether or not the test data of the selected memory blocks are identical, and outputting a pass signal or fail signal as a flag signal; and an output selection unit for selecting any one of the selected memory blocks as an output memory block, and changing the output memory block whenever the fail signal is generated from the comparison unit, thus forming it as a data output path, which may lessen error occurrence. | 02-05-2009 |