Patent application number | Description | Published |
20100038765 | Semiconductor package and method for manufacturing the same - Provided is a semiconductor package and a method for fabricating the semiconductor package. The semiconductor package may include a first package having a first semiconductor chip mounted on a first substrate and a second package having a second semiconductor chip mounted on a second substrate, the second substrate being bent to cover a side of the first package to contact the first substrate such that the first and second packages are connected electrically. | 02-18-2010 |
20110057297 | SEMICONDUCTOR CHIPS HAVING GUARD RINGS AND METHODS OF FABRICATING THE SAME - Provided is a semiconductor chip. The semiconductor chip includes a semiconductor substrate including a main chip region and a scribe lane region surrounding the main chip region. An insulating layer is disposed over the semiconductor substrate. A guard ring is disposed in the insulating layer in the scribe lane region. The guard ring surrounds at least a portion of the main chip region. The guard ring has a brittleness greater than a brittleness of the insulating layer. | 03-10-2011 |
20140374900 | SEMICONDUCTOR PACKAGE AND METHOD OF FABRICATING THE SAME - A semiconductor package includes memory I/O bumps and power/ground voltage bumps which are disposed at different positions from each other. In the semiconductor package, memory chips are disposed side by side, and a passivation layer is interposed between a conductive pad and a bump. | 12-25-2014 |
20150028477 | SEMICONDUCTOR PACKAGES HAVING SEMICONDUCTOR CHIPS DISPOSED IN OPENING IN SHIELDING CORE PLATE - A semiconductor package includes a first plate having a through hole therein, at least one interconnection layer disposed on a first surface of the first plate, and at least one semiconductor chip disposed on the at least one interconnection layer in a space defined by the through hole and electrically connected to the least one interconnection layer. The package further includes a second plate disposed on the at least one semiconductor chip and a second surface of the first plate on a side of the first plate opposite the first surface, and at least one conductive pad disposed on the second surface of the first plate and electrically connected to the at least one interconnection layer. | 01-29-2015 |
20150035148 | SEMICONDUCTOR PACKAGES AND METHODS OF FABRICATING THE SAME - A semiconductor package including a lower package including a lower package substrate and a lower semiconductor chip, the lower package substrate including an interconnection part and a core part, the core part including connection vias exposed by openings, the lower semiconductor chip buried in the core part, an upper package including an upper package substrate, an upper semiconductor chip provided on the upper package substrate, and solder balls provided on a bottom surface of the upper package substrate, and an intermetallic compound layer at an interface between the connection vias and the solder balls in the openings may be provided. | 02-05-2015 |
20150084170 | SEMICONDUCTOR PACKAGE AND METHOD OF FABRICATING THE SAME - Provided is a semiconductor package including a lower package, an interposer on the lower package, and an upper package on the interposer. The lower package may include a lower package substrate, a lower semiconductor chip on the lower package substrate, and a lower heat-transfer layer on the lower semiconductor chip. The interposer may include an interposer substrate, first and second heat-transfer openings defined by recessed bottom and top surfaces, respectively, of the interposer substrate, an upper interposer heat-transfer pad disposed in the second heat-transfer opening, and an upper heat-transfer layer disposed on the upper interposer heat-transfer pad. The upper package may include an upper package substrate, an upper package heat-transfer pad, which may be disposed in a third heat-transfer opening defined by a recessed bottom surface of the upper package substrate, and an upper semiconductor chip disposed on the upper package substrate. | 03-26-2015 |
Patent application number | Description | Published |
20080242056 | SYSTEM AND METHOD FOR CUTTING USING A VARIABLE ASTIGMATIC FOCAL BEAM SPOT - A variable astigmatic focal beam spot is formed using lasers with an anamorphic beam delivery system. The variable astigmatic focal beam spot can be used for cutting applications, for example, to scribe semiconductor wafers such as light emitting diode (LED) wafers. The exemplary anamorphic beam delivery system comprises a series of optical components, which deliberately introduce astigmatism to produce focal points separated into two principal meridians, i.e. vertical and horizontal. The astigmatic focal points result in an asymmetric, yet sharply focused, beam spot that consists of sharpened leading and trailing edges. Adjusting the astigmatic focal points changes the aspect ratio of the compressed focal beam spot, allowing adjustment of energy density at the target without affecting laser output power. Scribing wafers with properly optimized energy and power density increases scribing speeds while minimizing excessive heating and collateral material damage. | 10-02-2008 |
20100301027 | SYSTEM AND METHOD FOR CUTTING USING A VARIABLE ASTIGMATIC FOCAL BEAM SPOT - A variable astigmatic focal beam spot is formed using lasers with an anamorphic beam delivery system. The variable astigmatic focal beam spot can be used for cutting applications, for example, to scribe semiconductor wafers such as light emitting diode (LED) wafers. The exemplary anamorphic beam delivery system comprises a series of optical components, which deliberately introduce astigmatism to produce focal points separated into two principal meridians, i.e. vertical and horizontal. The astigmatic focal points result in an asymmetric, yet sharply focused, beam spot that consists of sharpened leading and trailing edges. Adjusting the astigmatic focal points changes the aspect ratio of the compressed focal beam spot, allowing adjustment of energy density at the target without affecting laser output power. Scribing wafers with properly optimized energy and power density increases scribing speeds while minimizing excessive heating and collateral material damage. | 12-02-2010 |