| Patent application number | Description | Published |
|---|
| 20080252341 | CLOCK SIGNAL DISTRIBUTION CIRCUIT AND INTERFACE APPARATUS USING THE SAME - A clock signal distribution circuit comprises a voltage control and distribution circuit configured to change a delay of a received clock signal in response to a control voltage and to generate a distributed clock signal, and control voltage generation circuit configured to generate the control voltage using a phase difference between received data and the distributed clock signal. | 10-16-2008 |
| 20080252353 | VOLTAGE MEASURING APPARATUS FOR SEMICONDUCTOR INTEGRATED CIRCUIT AND VOLTAGE MEASURING SYSTEM HAVING THE SAME - A voltage measuring apparatus for a semiconductor integrated circuit includes a first delay unit configured to delay a reference clock in a first region, a second delay unit configured to delay the reference clock in a second region and an analysis unit configured to analyze a difference in voltage level between the regions based on the phases of associated with the delayed clock signals generated by the first and second delay units. | 10-16-2008 |
| 20090002040 | DLL CIRCUIT OF SEMICONDUCTOR MEMORY APPARATUS - A DLL circuit for a semiconductor memory apparatus includes a delay line having a coarse delay chain, which has a plurality of coarse delayers connected in series and is inputted with a reference clock signal, and a plurality of fine delayers which receive output clock signals of the respective coarse delayers, and a delay control section for comparing phases of an output clock signal of a final coarse delayer among the coarse delayers with the reference clock signal and generating coarse control signals for controlling the coarse delayers and for comparing phases of an output clock signal of a fine delayer inputted with the output clock signals of the final coarse delayer, as a fine feedback clock signal, with the reference clock signal and generating fine control signals for controlling the fine delayers. | 01-01-2009 |
| 20090041154 | APPARATUS FOR TRANSMITTING SIGNAL IN SEMICONDUCTOR INTEGRATED CIRCUIT - An apparatus for transmitting a signal in a semiconductor integrated circuit includes a multilevel transmission control block that outputs a plurality of bits of an input signal in serial or parallel according to whether a multilevel transmission operation is performed or not, and a signal processing block that selectively performs the multilevel transmission operation according to a form of the input signal, which are output in serial or parallel from the multilevel transmission control block. | 02-12-2009 |
| 20090041172 | PHASE DETECTION CIRCUIT - A phase detection circuit includes a phase frequency detector for comparing a first input signal and a second input signal and outputting a first phase comparison signal and a second phase comparison signal, and a sensing circuit for sensing a pulse width difference between the first phase comparison signal and the second phase comparison signal and outputting phase detection signals which have different logic values. | 02-12-2009 |
| 20090097608 | PHASE DETECTING CIRCUIT AND CLOCK GENERATING APPARATUS INCLUDING THE SAME - A phase detecting circuit includes a first node that outputs a pull-up control signal, a second node that outputs a pull-down control signal, an initializing unit that initializes voltage levels of the first and second nodes in response to a pre-charge signal, a data input unit to which receives a receiver data, a phase comparison unit that compares a phase of a receiver clock and a phase of the receiver data input to the data input unit to control the voltage levels of the first and second nodes, and a charging/discharging unit that charges or discharges electric charges that are applied to the first and second nodes. | 04-16-2009 |
| 20100277209 | SIGNAL RECEIVER CIRCUIT CAPABLE OF IMPROVING AREA AND POWER EFFICIENCY IN SEMICONDUCTOR INTEGRATED CIRCUITS - A signal receiver circuit includes a first level detector for offset-controlling a first output node in response to a pair of first reference signals. A second level detector offset-controls a second output node in response to a pair of second reference signals. | 11-04-2010 |
