Patent application number | Description | Published |
20090003106 | Precharge control circuit - A precharge control circuit includes a precharge control unit and a precharge unit. The precharge control unit controls and outputs a precharge signal in response to a read command signal, a write command signal, and a first signal. The precharge unit precharges local input/output lines in response to a signal output from the precharge control unit. | 01-01-2009 |
20090168564 | Strobe signal controlling circuit - A strobe signal controlling circuit is provided which includes an initial write controller configured to outputs a write pulse signal, which is activated in a write command, in synchronization with a clock signal, a DQS signal outputting unit configured to outputs a write DQS signal by synchronizing an output signal of the initial write controller to the clock signal, a control signal generator configured to generates a control signal in response to the output signal of the initial write controller, and a reset signal generator configured to responds to a reset signal and a DQS enable signal to output a reset signal to the DQS signal outputting module in synchronization with the control signal. | 07-02-2009 |
20100027358 | Semiconductor memory device capable of read out mode register information through DQ pads - A semiconductor memory device is provided that is capable of reading out mode register information stored in a register adapted for LPDDR2 (Low Power DDR2), through DQ pads. The semiconductor memory device includes a mode register control unit configured to receive address signals, a mode register write signal and a mode register read signal and generate a flag signal and at least one output information signal, and a global I/O line latch unit for transferring the output information signal to a global I/O line in response to the flag signal. | 02-04-2010 |
20100141309 | Initialization circuit and bank active circuit using the same - An initialization circuit comprises a section signal generator generating a section signal, of which a prescribed section is enabled in response to a power-up signal, a first oscillator generating a first period signal in response to the section signal, a first period multiplier generating a first multiplied signal by multiplying a period of the first period signal, and a signal selector transferring the first multiplied signal or a second multiplied signal selectively as a self-refresh enable signal in response to the section signal. | 06-10-2010 |
20100141333 | Reservoir capacitor array circuit - A reservoir capacitor array circuit capable of allowing an internal voltage to be maintained stably, comprises a plurality of reservoir capacitors, each of the reservoir capacitors including a switch element which is connected between a power source voltage and a prescribed node and switched in response to a test enable signal which is enabled depending on a test mode signal or whether the fuse is cut or not, and a capacitor connected between the node and a ground voltage. | 06-10-2010 |
20100142305 | Source control circuit and semiconductor memory device using the same - A source control circuit comprises a control signal generating unit for generating a standby signal which is enabled in a standby condition, and a switching unit connected between a power line for supplying power to an internal circuit and an external power and controlling the supply of the external power in response to the standby signal. | 06-10-2010 |
20100157716 | Sub word line driving circuit - A sub word line driving circuit includes a FX driver which buffers an inverted FX signal to generate a FX signal in response to a control signal, and a sub word line driver which is supplied with the FX signal and receives a main word line signal to drive a sub word line signal. | 06-24-2010 |
20110310677 | Semiconductor Memory Device Capable of Read Out Mode Register Information Through DQ Pads - A semiconductor memory device is provided that is capable of reading out mode register information stored in a register adapted for LPDDR2 (Low Power DDR2), through DQ pads. The semiconductor memory device includes a mode register control unit configured to receive address signals, a mode register write signal and a mode register read signal and generate a flag signal and at least one output information signal, and a global I/O line latch unit for transferring the output information signal to a global I/O line in response to the flag signal. | 12-22-2011 |
20120256663 | INITIALIZATION CIRCUIT AND BANK ACTIVE CIRCUIT USING THE SAME - An initialization circuit comprises a section signal generator generating a section signal, of which a prescribed section is enabled in response to a power-up signal, a first oscillator generating a first period signal in response to the section signal, a first period multiplier generating a first multiplied signal by multiplying a period of the first period signal, and a signal selector transferring the first multiplied signal or a second multiplied signal selectively as a self-refresh enable signal in response to the section signal. | 10-11-2012 |