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Jong-Wan
Jong-Wan Choi, Gyeonggi-Do KR
| Patent application number | Description | Published |
|---|---|---|
| 20080206954 | METHODS OF REDUCING IMPURITY CONCENTRATION IN ISOLATING FILMS IN SEMICONDUCTOR DEVICES - A method of fabricating a semiconductor device includes forming a lower device on a lower semiconductor substrate, and forming an interlayer insulating film on the lower device. An upper semiconductor substrate is formed on the interlayer insulating film such that the interlayer insulating film is between the lower and upper semiconductor substrates. Upper trenches are formed within the upper semiconductor substrate. An upper device isolating film is formed within the upper trenches. The upper device isolating film is irradiated with ultraviolet light having a wavelength configured to break chemical bonds of impurities in the upper device isolating film to reduce an impurity concentration thereof. | 08-28-2008 |
| 20100167490 | Method of Fabricating Flash Memory Device - Provided are methods of fabricating flash memory devices that may prevent a short circuit from occurring between cell gate lines. Methods of fabricating such flash memory devices may include forming gate lines including a series of multiple cell gate lines and multiple selection gate lines. Each gate line may include a stacked structure of a tunnel insulating layer, a floating gate, a gate insulating layer, and/or a polysilicon layer operable to be a control gate, all formed on a semiconductor substrate. Methods may include forming a first insulating layer that selectively fills gaps between the cell gate lines from the bottom up and between adjacent ones of the cell gate lines and the selection gate lines, and does not fill a space located on outer sides of the selection gate lines that are opposite the plurality of cell gate lines. A spacer may be formed on the outer sides of the selection gate lines that are opposite to the cell gate lines, after forming the first insulating layer. A second insulating layer may be formed in a space where the spacer is formed. | 07-01-2010 |
Jong-Wan Choi, Seoul KR
| Patent application number | Description | Published |
|---|---|---|
| 20100055212 | COSMETIC COMPOSITION COMPRISING TISSUE CULTURED PANAX GINSENG C.A. MEYERADVENTITIOUS ROOT ITSELF AND A PREPARING METHOD THEREOF - The present invention relates to a cosmetic composition comprising tissue-cultured adventitious roots itself of ginseng, and to a preparing method thereof. The cosmetic composition of the present invention is characterized in that effective ingredients are dip-extracted from the tissue cultured adventitious roots of a ginseng contained in the composition, without any additional process for preparing an extract of the tissue-cultured adventitious roots of a ginseng. In the cosmetic composition of the present invention, the effective ingredients are naturally and continuously dip-extracted from the tissue-cultured adventitious roots itself of a ginseng and maintained, and also allows a user to recognize visually the presence of the adventitious roots of a ginseng, thereby giving trust of the presence of the effective ingredient to the user, and improving user's satisfaction through its natural flavor. Further, the preparing method for the cosmetic composition is a simple and inexpensive process without any additional step, such as extraction, isolation and purification, and further has an advantage that an effective ingredient is dip-extracted from the adventitious roots itself of ginseng while not losing an effective ingredient. | 03-04-2010 |
Jong-Wan Choi, Suwon-Si KR
| Patent application number | Description | Published |
|---|---|---|
| 20090020847 | Semiconductor device having trench isolation region and methods of fabricating the same - A semiconductor device having a trench isolation region and methods of fabricating the same are provided. The method includes forming a first trench region in a substrate, and a second trench region having a larger width than the first trench region in the substrate. A lower material layer may fill the first and second trench regions. The lower material layer may be etched by a first etching process to form a first preliminary lower material layer pattern remaining in the first trench region and form a second preliminary lower material layer pattern that remains in the second trench region. An upper surface of the second preliminary lower material layer pattern may be at a different height than the first preliminary lower material layer pattern. The first and second preliminary lower material layer patterns may be etched by a second etching process to form first and second lower material layer patterns having top surfaces at substantially the same height. First and second upper material layer patterns may be formed on the first and second lower material layer patterns, respectively. | 01-22-2009 |
| 20090045483 | Semiconductor devices having trench isolation regions and methods of manufacturing semiconductor devices having trench isolation regions - A semiconductor device may include a semiconductor substrate, trench region, buffer pattern, gap fill layer, and transistor. The trench region may be provided in the semiconductor substrate to define an active region. The buffer pattern and gap fill layer may be provided in the trench region. The buffer pattern and gap fill layer may fill the trench region. The gap fill layer may be densified by the buffer pattern. The transistor may be provided in the active region. A method of manufacturing a semiconductor device may include: forming a trench region in a semiconductor substrate; forming a buffer layer on an inner wall of the first trench region; forming a gap fill layer, filling the trench region; performing a thermal process to react the impurity with the oxygen, forming a buffer pattern; and forming a transistor in the active region. | 02-19-2009 |
| 20090191687 | METHOD OF FILLING A TRENCH AND METHOD OF FORMING AN ISOLATING LAYER STRUCTURE USING THE SAME - A method of filling a trench in a substrate ensures that a void or seam is not left in the material occupying the trench. First, a preliminary insulating layer is formed so as to extend contiguously along the bottom and sides of the trench and along an upper surface of the substrate. Impurities are then implanted into a portion of the preliminary insulating layer adjacent the top of the first trench to form a first insulating layer having a doped region and an undoped region. The doped region is removed to form a first insulating layer pattern at the bottom and sides of the first trench, and which first insulating layer pattern defines a second trench. The second trench is then filled with insulating material. | 07-30-2009 |
Jong-Wan Jung, Gyeonggi-Do KR
| Patent application number | Description | Published |
|---|---|---|
| 20090166696 | CMOS Image Device with Local Impurity Region - According to a CMOS image device and a method of manufacturing same, dark current is decreased by a local impurity region. The image device includes a semiconductor substrate, and a transfer gate formed on a predetermined portion of the semiconductor substrate and electrically insulated from the semiconductor substrate. A photodiode is formed in the semiconductor substrate on one side of the transfer gate, and a floating diffusion region is formed on the semiconductor substrate in the other side of the transfer gate. A local impurity region of a first conductivity type is formed to be partially overlapped the transfer gate between the photodiode and the floating diffusion region. | 07-02-2009 |