| Patent application number | Description | Published |
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| 20100006625 | COMPOSITION AND METHODS OF FORMING SOLDER BUMP AND FLIP CHIP USING THE SAME - Provided are a composition for an anisotropic conductive adhesive, a method of forming a solder bump and a method of forming a flip chip using the same. The composition for an anisotropic conductive adhesive includes a low melting point solder particle and a thermo-curable polymer resin. The anisotropic conductive adhesive includes forming a mixture by mixing a polymer resin and a curing agent, and mixing a deforming agent, a catalyst or a reductant with the mixture. | 01-14-2010 |
| 20100073238 | MICROSTRIP PATCH ANTENNA WITH HIGH GAIN AND WIDE BAND CHARACTERISTICS - Provided is a microstrip patch antenna. The microstrip patch antenna includes a dielectric layer, a feed circuit disposed in the dielectric layer, at least one slot disposed in the dielectric layer and vertically spaced apart from the feed circuit, and a patch antenna disposed outside the dielectric layer and vertically spaced apart from the at least one slot. | 03-25-2010 |
| 20110018670 | ELECTRONIC DEVICE INCLUDING LTCC INDUCTOR - Provided is an electronic device that includes an LTCC inductor including a first sheet disposed on a substrate and including a first conductive pattern, a second sheet disposed on the first sheet and including a second conductive pattern, and a via electrically connecting the first conductive pattern to the second conductive pattern, and a spacer disposed on a lower surface of the first sheet to provide an air gap between the substrate and the first sheet, wherein the first conductive pattern is exposed out of the lower surface of the first sheet. | 01-27-2011 |
| 20110090651 | PACKAGE STRUCTURE - Provided is a package structure. The package structure includes a first substrate, a first device, a second substrate, a first via contact, and at least one second device. The first device is formed on the first substrate. The second substrate has an air gap over the first substrate and covers the first device. The first via contact is connected to the first device through the second substrate. At least one second device is electrically connected to the first via contact, and is stacked on the second substrate. | 04-21-2011 |
| 20110115036 | DEVICE PACKAGES AND METHODS OF FABRICATING THE SAME - Provided is a method for fabricating a device package. The method includes: preparing a substrate where respectively corresponding device structures and input and output pads are disposed on an active surface; preparing a carrier substrate where a metal lid corresponding to the device structure is disposed on one surface; and contacting the active surface of the substrate with the metal lid of the carrier substrate to cover and seal the device structure corresponding to the metal lid. | 05-19-2011 |
| Patent application number | Description | Published |
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| 20080285978 | OPTICAL HYBRID MODULE - Provided is an optical hybrid module in which an optical device, a filter, an amplifier and an antenna are hybrid-integrated, which includes: a silicon optical bench disposed on a substrate and having an optical fiber and an optical device; an amplifier disposed on the substrate and connected to the optical device disposed on the silicon optical bench to amplify a signal transmitted from the optical device; and an antenna disposed on the substrate to be connected to the amplifier and transmitting a signal amplified by the amplifier. Thus, a foot-print module may be embodied by disposing an antenna and a filter on a single- or multi-layer substrate and providing a bias required for the optical device and the amplifier through a solder ball. Also, due to the antenna and filter disposed on the substrate, an expensive connector is not needed, and thus a production costs can be reduced. | 11-20-2008 |
| 20080297299 | VERTICALLY FORMED INDUCTOR AND ELECTRONIC DEVICE HAVING THE SAME - Provided are an inductor, which is vertically formed, and an electronic device having the inductor, and more particularly, an inductor capable of minimizing loss of a surface area and accomplishing high efficiency impedance by vertically forming the inductor in a plurality of insulating layers, and an electronic device having the same. The inductor includes a plurality of conductive lines disposed in the insulating layers; and vias vertically formed in the insulating layers to electrically connect the plurality of conductive lines. When a board or an electronic device including an inductor proposed by the present invention is manufactured, the inductor can occupy a minimum area in the electronic device or board while providing high inductance. In particular, the surface area of the electronic device or board occupied by the inductor can be remarkably decreased to reduce manufacturing costs. | 12-04-2008 |
| 20090261481 | WAFER LEVEL PACKAGE AND METHOD OF FABRICATING THE SAME - Provided are a wafer level package in which a communication line can be readily formed between an internal device and the outside of the package, and a method of fabricating the wafer level package. The wafer level package includes a first substrate having a cavity in which a first internal device is disposed, an Input/Output (I/O) pad formed on the first substrate and electrically connected with the first internal device, a second substrate disposed over the first substrate and from which a part corresponding to the I/O pad is removed, and a solder bonding the first and second substrates. According to the wafer level package and the method of fabricating the same, upper and lower substrates are sawed to different cutting widths, or a hole is formed in the upper substrate, such that a communication line of an internal device can be readily formed without a via process which penetrates a substrate. Therefore, in comparison with a conventional wafer level package fabricated using the via process, it is possible to simplify a fabrication process and reduce production cost. | 10-22-2009 |
| 20100320596 | METHOD FOR FABRICATING SEMICONDUCTOR PACKAGE AND SEMICONDUCTOR PACKAGE USING THE SAME - Provided is a method for fabricating semiconductor package and a semiconductor package fabricated using the same. The method for fabricating semiconductor package dopes a mixture including the polymer material and the solder particle on the substrate in which the terminal is formed and applies heat, and thus the solder particle flows (or diffuses) toward the terminal in the heated polymer resin to adhere to the exposed surface of the terminal, i.e., the side surface and upper surface of the terminal, thereby forming the solder layer. The solder layer improves the adhesive strength between the terminal of the semiconductor chip and the terminal of the substrate in the subsequent flip chip bonding process. | 12-23-2010 |
