| Patent application number | Description | Published |
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| 20080222369 | Access Control Partitioned Blocks in Shared Memory - A method for controlling multiple access to partitioned areas of a shared memory and a digital processing apparatus having the shared memory are disclosed. According to embodiments of the present invention, the storage area of a shared memory is partitioned to a plurality of storage areas, and each processor accesses a storage area through each access port to store data and transfers an authority to access the pertinent storage area to the other processor, thereby allowing access by the other processor. With the present invention, the data communication time between the plurality of processors can be minimized, and the process efficiency of each processor can be optimized. | 09-11-2008 |
| 20080263286 | Operation Control of Shared Memory - A method of controlling a shared memory and a user terminal controlling the operation of the shared memory are disclosed. The portable terminal according to an embodiment of the present invention has a memory unit with a storage area partitioned to blocks in a quantity of n and a plurality of processors reading or writing data by accessing a partitioned block. At least one of the partitioned blocks is assigned as a common storage area, accessible by a processor having an access privilege, and the processor having the access privilege performs an operation of maintaining the data stored in the common storage area. With the present invention, the common storage area can be accessed by a plurality of processors, and thus the data transmission time between the processors can be minimized. | 10-23-2008 |
| 20080263429 | Method and Device for Correcting Code Data Error - A method and a device for correcting a code data error are disclosed. A main processor included in a digital processing device in accordance with an embodiment of the present invention writes in a shared memory third code data error-corrected by a predetermined error correcting method or second code data written in a backup area if there is an error in first code data written in a code data area of a nonvolatile memory. The main processor or an application processor performs an operation corresponding to the third code data. With the present invention, a system can be stably operated thanks to promptly dealing with an error when the error in boot codes is detected or generated | 10-23-2008 |
| 20080288711 | Multimedia Platform - A device comprising a multimedia platform with a plurality of memories and a method of sharing a non-volatile memory. The multimedia platform in accordance with an embodiment of the present invention can have a non-volatile memory, a multimedia processor setting a route in accordance with a route selection signal received from the main processor such that the main processor accesses the non-volatile memory or the display unit, a first volatile memory which is a temporary memory device of the main processor, and a second volatile memory which is a temporary memory of the multimedia processor. With the present invention, the portable terminal can be made smaller by putting a memory chip and a multimedia platform in a single chip by use of the POP (package on package) technology. | 11-20-2008 |
| 20090019248 | PORTABLE DEVICE AND METHOD FOR CONTROLLING SHARED MEMORY IN PORTABLE DEVICE - A portable terminal and a method of controlling a shared memory, the portable terminal are disclosed. The portable terminal includes a memory unit, being equipped with at least 2 ports and having a storage block partitioned into partitioned blocks in a quantity of n, and a plurality of processors, reading or writing data by accessing a particular partitioned block through each dedicated port. At least one of the partitioned blocks is assigned to a common storage block, accessible by a processor having an access privilege, and the access privilege is transferred between the plurality of processors. The common storage block can be partitioned into k sub partitioned blocks, which the data type and process to be stored are predetermined. With the present invention, in the case of the common storage block for the plurality of processors, by allowing the partitioned storage blocks to be partitioned again into sub partitioned blocks depending on a type of data to be stored, the data processing/transmission speed and efficiency can be optimized. | 01-15-2009 |
| 20090043970 | DEVICE HAVING SHARED MEMORY AND METHOD FOR PROVIDING ACCESS STATUS INFORMATION BY SHARED MEMORY - A device having a shared memory and a method for providing access status information by the shared memory are disclosed. A digital processing device includes n processors and a shared memory. The shared memory is coupled to each processor though a separate bus, its storage area includes m common sections, and generates and outputs access status information related to whether an arbitrary processor is accessing at least one of the common sections. With the present invention, a control sequence of each processor can be simplified at a maximum by allowing the shared memory to generate and output access status information related to the common sections. | 02-12-2009 |
| 20090196438 | MULTIMEDIA PROCESSOR CHIP AND METHOD FOR PROCESSING AUDIO SIGNALS - A multimedia processor chip includes: a first re-sampler converting a sample rate of a decoded first audio signal into a first sample rate and outputting the converted first audio signal to a first output buffer; a second re-sampler converting a sample rate of a decoded second audio signal into the first sample rate and outputting the converted second audio signal to a second output buffer; and a mixer mixing the audio signals input from the first output buffer and the second output buffer and outputting the mixed audio signals to an audio converter through a communication unit. Accordingly, it is possible to reduce a processing load of a multimedia processor core to permit a low-power operation and to easily accomplish various audio effects. | 08-06-2009 |
| 20090201256 | PORTABLE TERMINAL HAVING INPUTTING MEANS USING IMAGE SENSOR - The present invention is directed to a portable terminal having inputting means using an image sensor and its input method. The portable terminal according to an embodiment of the present invention comprises a transparent solid plate mounted in a keypad area; an image sensor having unit cells of lattice type outputting an electrical signal corresponding to the light irradiated through the transparent solid plate; and a key selection recognizer generating and outputting a key button selection signal corresponding to the location of a unit cell that outputted the least electrical signal value by making reference to the size of the value of the electrical signal inputted from the unit cells. The present invention enables compacting of portable terminals owing to eliminating the need to design key buttons to match the size of human fingers. | 08-13-2009 |
| 20090204770 | DEVICE HAVING SHARED MEMORY AND METHOD FOR CONTROLLING SHARED MEMORY - A device having a shared memory and a shared memory controlling method are disclosed. A digital processing device can include a shared memory, having a storage area including at least one common section, coupled to each of the processors through separate buses and outputting access information to whether a processor is accessing a common section. With the present invention, each processor can efficiently use or/and control a shared memory by using access information. | 08-13-2009 |
| 20090254686 | MEMORY SHARING THROUGH A PLURALITY OF ROUTES - A method for sharing a memory through a plurality of routes and a device thereof are disclosed. The digital processing apparatus in accordance with an embodiment of the present invention comprises a main processor, an application processor controlled by the main processor and coupled to the main processor through one connection bus and a memory having a plurality of ports, each of which is coupled to the application processor through an independent memory bus. With the present invention, the process time for processing a high-performance, high-resolution image can be minimized, and the loss in process efficiency of the application processor can be minimized. | 10-08-2009 |
| 20090254713 | ACCESS CONTROL TO PARTITIONED BLOCKS IN SHARED MEMORY - A method for controlling multiple access to partitioned areas of a shared memory and a portable terminal having the shared memory are disclosed. According to an embodiment of the present invention, the storage area of a shared memory is partitioned to a plurality of storage areas, and each control unit accesses a storage area through each access port to store data and transfers an authority to access the pertinent storage area to the other control unit, thereby allowing access by the other control unit. With the present invention, the data communication time between the plurality of control units can be minimized, and the process efficiency of each control unit can be optimized. | 10-08-2009 |
| 20090254715 | VARIABLE PARTITIONED BLOCKS IN SHARED MEMORY - A method and device for varying the size of partitioned areas of a shared memory is disclosed. The present invention resets the size of partitioned areas by expanding the size of a shared area when data that is larger than the writable area of the shared area is to be written, after the storage area of a memory unit is partitioned to a plurality of partitioned areas by a main control unit. The memory unit is coupled with a main control unit and a supplementary control unit through independent ports. With the present invention, the data communication time between control units for processing data can be minimized, and the operation speed of each control unit can be optimized. | 10-08-2009 |
| 20100005284 | DEVICE HAVING SHARED MEMORY AND METHOD FOR TRANSFERRING CODE DATA - The present invention relates to a device having a shared memory and a code data transmitting method. According to an embodiment of the present invention, the digital processing device can include n processors, n being a natural number of 2 or greater; and a shared memory, coupled to each of the processors through independent buses and having a boot section allotted, the boot section being for writing a boot program code to be used for booting of at least one processor. | 01-07-2010 |
| 20100115170 | CHIP COMBINED WITH PROCESSOR CORES AND DATA PROCESSING METHOD THEREOF - A chip having integrated multiple processor cores and a data processing method are disclosed. The processor chip includes an MP core (main processor core), an AP core (application processor core) which performs a processing function designated by a control of the MP core, a first SM controller which sets a path such that the MP core is coupled with a shared memory, and a second SM controller which sets a path such that the AP core is coupled with the shared memory. By virtue of the present invention, the number of chips installed can be minimized, to allow efficient utilization of PCB space and enable a compact size for a portable terminal. | 05-06-2010 |
