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| 20100006821 | NANOSCALE MULTI-JUNCTION QUANTUM DOT DEVICE AND FABRICATION METHOD THEREOF - The present invention relates to a method of fabricating a nanoscale multi-junction quantum dot device wherein it can minimize constraints depending on the number or shape of patterns and a line width, and in particular, overcome shortcomings depending on the proximity effect occurring between patterns while employing the advantages of electron beam lithography to the utmost by forming a new conductive layer between the patterns and utilizing it as a new pattern. | 01-14-2010 |
| 20110174620 | ULTRA HIGH SPEED AND HIGH SENSITIVITY DNA SEQUENCING SYSTEM AND METHOD FOR SAME - The present system relates to a system architecture that uses a single electron transistor (SET) to analyze base sequences of deoxyribonucleic acid (DNA) at ultra high speed in real time. DNA represents the entire body of genetic information and consists of nucleotide units. There are a total of four types of nucleotides, and each nucleotide consists of an identical pentose (deoxyribose), phosphate group, and one of four types of bases (Adenine: A, Guanine: G, Cytosine: C, Thymine: T). A and G are purines having a bicyclic structure while C and T are pyrimidines having a monocyclic structure. Each has a different atomic arrangement, which signifies a different charge distribution from one another. Therefore, a system comprising a single electron transistor that is very sensitive to charges, a probe of a very small size that reacts to one nucleotide very effectively, and an extended gate that connects the SET with the probe, can be used to analyze DNA base sequences at ultra high speed in real time. | 07-21-2011 |
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| 20080203507 | Image sensors for zoom lenses and fabricating methods thereof - An image sensor includes a semiconductor substrate on which a plurality of photo diodes are formed. A plurality of interlayer dielectrics are formed above the semiconductor substrate, and a plurality of metal lines are formed on each of the interlayer dielectrics. A plurality of micro lenses are formed above the uppermost one of the interlayer dielectrics. The light passing through the zoom lenses is incident on the respective micro lenses. The plurality metal lines formed on at least one of the plurality of interlayer dielectrics have the same width. | 08-28-2008 |
| 20080224191 | Image pickup device with prevention of leakage current - An image pickup device includes an active pixel sensor (APS), a row driver, and a leakage current breaker. The active pixel sensor includes an array of a plurality of pixels. The row driver selects at least one pixel to be activated to output signals. The leakage current breaker decreases the leakage current through the unselected pixels by applying a leakage current breaker voltage at the bit lines of the APS array. | 09-18-2008 |
| 20090174799 | Method of driving an image sensor - For driving an image sensor having a pixel with a transfer gate formed between a photo-detector and a floating diffusion region, a noise-reducing voltage is applied on the transfer gate during a first period of an integration mode. A blooming current voltage is applied on the transfer gate during a second period of the integration mode. A read voltage is applied on the transfer gate during a read mode after the integration mode. The read voltage has a higher magnitude than the blooming current voltage. With application of the noise-reducing voltage, noise is reduced and a dynamic range is extended for the image sensor. | 07-09-2009 |
| 20090230444 | CMOS IMAGE SENSOR CONFIGURED TO PROVIDE REDUCED LEAKAGE CURRENT - A complementary metal-oxide-semiconductor (CMOS) image sensor (CIS) includes a semiconductor substrate including a photodiode therein as a light sensing unit. A floating diffusion region of a first conductivity type is provided in the semiconductor substrate, and is configured to receive charges generated in the photodiode. A power supply voltage region of the first conductivity type is also provided in the semiconductor substrate. A reset transistor including a reset gate electrode on a surface of the substrate between the floating diffusion region and a power supply voltage region is configured to discharge charges stored in the floating diffusion region in response to a reset control signal. The reset transistor includes a channel region in the substrate extending between the floating diffusion region and the power supply voltage region such that the floating diffusion region and the power supply voltage regions define source/drain regions for the reset transistor. An impurity region is provided in a first portion of the channel region adjacent to the floating diffusion region. The impurity region has a doping such that the first portion of the channel region adjacent to the floating diffusion region has a different built-in potential than a second portion of the channel region adjacent to the power supply voltage region. | 09-17-2009 |
| 20100056864 | CAPSULE-TYPE IMAGE PHOTOGRAPHING APPARATUS AND ENDOSCOPY USING THE SAME - Provided are a capsule-type image photographing apparatus and endoscopy using the same. The apparatus includes a shell unit having a globular shape and a main body unit capable of freely rotating in the shell unit. The main body unit includes an image photographing system, a wireless transmitter, a battery, a counterweight for determining the center of gravity of the main body unit, and an encapsulant for fixing the image photographing system, the wireless transmitter, the battery, and the counterweight. The apparatus may be a long-distance capsule-type image photographing apparatus or a short-distance capsule-type image photographing apparatus depending on the position of the counterweight. By use of the long- and short-distance capsule-type image photographing apparatuses, the interior of the tested person's body can be effectively photographed. | 03-04-2010 |
| 20100070821 | METHOD AND APPARATUS FOR DETECTING FREE PAGE AND A METHOD AND APPARATUS FOR DECODING ERROR CORRECTION CODE USING THE METHOD AND APPARATUS FOR DETECTING FREE PAGE - A method and apparatus for detecting a free page of a memory device, and a method and apparatus for decoding an error correction code by using the method and apparatus for detecting a free page are provided. Free page data read from the memory is converted into a converted codeword for inclusion as an element of an error correction code field. The converted codeword is compared to an initially set target codeword to detect an amount of non-identical bits. A page read from the memory is determined to be a free page when the amount of non-identical bits is equal to or less than an initially set threshold value. | 03-18-2010 |
| 20100233073 | Manufacturing Method of Highly Pure Alpha-LiAlO2 - The present invention relates to a method for preparing high-purity alpha-lithium aluminate (α-LiAlO | 09-16-2010 |
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| 20100021108 | OPTICAL WAVEGUIDE DEVICE AND OPTICAL COMMUNICATION MODULE - An optical waveguide device and an optical communication module are provided. In the optical waveguide device which includes a core and a cladding layer formed around the core and has one end formed to be inclined so as to refract input and output signals, the core includes therein a diffraction portion for diffracting an optical signal incident through the cladding layer to propagate straight through the core. Thus, it is possible to prevent deterioration of an optical signal coupling ratio in implementing a technique of transmitting optical signals in opposite directions. | 01-28-2010 |
| 20100086310 | BIDIRECTIONAL OPTICAL TRANSCEIVER - A bidirectional optical transceiver is disclosed. In the bidirectional optical transceiver, by implementing, as a stacked structure, an optical bench in which an optical system and an optical-transmitting module are installed and a multi-layer substrate with good thermal, electrical and high-resistance characteristics in which an optical-receiving module and a driving circuit for driving the optical-transmitting module are installed, thermal, electrical or optical crosstalk is prevented, high-speed transmission of transmission signals is possible through high-speed modulation thereof, and miniaturization is achieved. | 04-08-2010 |
| 20100136783 | METHOD OF MANUFACTURING THROUGH-VIA - Disclosed is a method of manufacturing a through-via. The through-via manufacturing method includes forming a core-via hole in a wafer, forming a suction-via hole adjacent to the core-via hole in the wafer, forming a via core in the core-via hole, forming a polymer-via hole connected to the suction-via hole in the wafer, filling the polymer-via hole with polymer solution by creating a vacuum inside the polymer-via hole by drawing air out of the suction-via hole, and polishing the wafer such that the via core formed in the core-via hole is exposed. | 06-03-2010 |
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| 20100012364 | METHOD OF MANUFACTURING ELECTRONIC COMPONENT EMBEDDED CIRCUIT BOARD - An electronic component embedded printed circuit board and a method for manufacturing the same are disclosed. The method includes: providing a first carrier having a first circuit pattern formed on one surface thereof; providing a second carrier having a second circuit pattern formed on one surface thereof; flip-chip bonding an electronic component to the first circuit pattern; stacking one side of an insulator on one side of the first carrier to cover the electronic component; compressing the second carrier having the second circuit pattern formed on one surface thereof on an other side of the insulator; and removing the first carrier and the second carrier. The method can improve the degree of conformation for an electrical component by embedding the electrical component using a flip-chip bonding method and can improve the yield by simplifying the production process. | 01-21-2010 |
| 20100059267 | PRINTED CIRCUIT BOARD AND METHOD OF MANUFACTURING THE SAME - A printed circuit board and a method of manufacturing the printed circuit board are disclosed. In an embodiment of the present invention, the method of manufacturing a printed circuit board can include: providing a pair of conductive layers, in which roughness of one surface of one of the pair of conductive layers is different from roughness of one surface of the other of the pair of conductive layers; and stacking the pair of the conductive layers on a dielectric layer such that one surface of one of the pair of conductive layers faces one surface of the dielectric layer and one surface of the other of the pair of conductive layers faces another surface of the dielectric layer. | 03-11-2010 |
| 20100090351 | ELECTRO COMPONENT PACKAGE - An electro component package is disclosed. The electro component package in accordance with an embodiment of the present invention includes a first package substrate having a first chip mounted on an upper surface thereof, the first chip having a through-via formed therein; a second package substrate being separated from the first package substrate and having a second chip mounted on an upper surface thereof; and a connection substrate having one end connected with an upper surface of the first chip and the other end connected with an upper surface of the second chip, the connection substrate electrically connecting the first chip with the second chip. | 04-15-2010 |
| 20100147575 | PRINTED CIRCUIT BOARD AND MANUFACTURING METHOD THEREOF - A printed circuit board and a method of manufacturing the printed circuit board are disclosed. The method of manufacturing a printed circuit board can include: processing a first hole, which has a tapered shape, in one side of a substrate by using a laser drill; processing a second hole, which has a tapered shape and which connects with the first hole, in the other side of the substrate by using a laser drill in a position corresponding to that of the first hole; and forming a conductive portion, which electrically connects both sides of the substrate through the first hole and the second hole, by performing plating. This method may be used for providing reliable interlayer connections. | 06-17-2010 |
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| 20080265304 | Nonvolatile semiconductor device including a floating gate, method of manufacturing the same and associated systems - A memory device includes a first floating gate electrode on a substrate between adjacent isolation layers in the substrate, at least a portion of the first floating gate protruding above a portion of the adjacent isolation layers, a second floating gate electrode, electrically connected to the first floating gate electrode, on at least one of the adjacent isolation layers, a dielectric layer over the first and second floating gate electrodes, and a control gate over the dielectric layer and the first and second floating gate electrodes. | 10-30-2008 |
| 20090253255 | Semiconductor device having a pair of fins and method of manufacturing the same - Example embodiments relate to a semiconductor device and a method of manufacturing the same. A semiconductor device according to example embodiments may have reduced disturbances during reading operations and a reduced short channel effect. The semiconductor device may include a semiconductor substrate having a body and a pair of fins protruding from the body. Inner spacer insulating layers may be formed on an upper portion of an inner sidewall of the pair of fins so as to reduce the entrance to the region between the pair of fins. A gate electrode may cover a portion of the external sidewalls of the pair of fins and may extend across the inner spacer insulating layers so as to define a void between the pair of fins. Gate insulating layers may be interposed between the gate electrode and the pair of fins. | 10-08-2009 |
| 20110156125 | NONVOLATILE SEMICONDUCTOR DEVICE INCLUDING A FLOATING GATE AND ASSOCIATED SYSTEMS - A memory device includes a first floating gate electrode on a substrate between adjacent isolation layers in the substrate, at least a portion of the first floating gate protruding above a portion of the adjacent isolation layers, a second floating gate electrode, electrically connected to the first floating gate electrode, on at least one of the adjacent isolation layers, a dielectric layer over the first and second floating gate electrodes, and a control gate over the dielectric layer and the first and second floating gate electrodes. | 06-30-2011 |
