| Patent application number | Description | Published |
|---|
| 20080219074 | Abbreviated Burst Data Transfers for Semiconductor Memory - An integrated circuit having a nominal minimum burst length defined by a nominal data prefetch size transfers data by accepting an abbreviated burst data read request directed to a first bank, prefetching less than the nominal data prefetch size, and providing the data in an abbreviated burst data transfer less than the nominal minimum burst length. | 09-11-2008 |
| 20080301391 | METHOD AND APPARATUS FOR MODIFYING A BURST LENGTH FOR SEMICONDUCTOR MEMORY - A method and apparatus for performing a burst access operation for a memory device. The method includes receiving a burst access command for the burst access operation and receiving a burst length modifying value for the burst access operation. A modified burst length is generated from a pre-programmed burst length using the burst length modifying value. The modified burst length is used for the burst access operation without changing the pre-programmed burst length. The burst access operation is performed with the modified burst length. | 12-04-2008 |
| 20080313494 | MEMORY REFRESH SYSTEM AND METHOD - A refresh scheduler is configured to refresh memory cells of a memory device according to a plurality of refresh intervals. The various refresh intervals are determined in response to refresh errors. | 12-18-2008 |
| 20090021995 | Early Write Method and Apparatus - A write operation is performed in a memory device. During a first stage of the write operation, a signal is applied to gating circuitry at a first voltage level for coupling a data bus line to a bit line when the data bus line is unmasked and for decoupling the data bus line from the bit line when the data bus line is masked. During one or more subsequent stages of the write operation, the signal voltage level is changed for enabling completion of the write operation. | 01-22-2009 |
| 20090031077 | INTEGRATED CIRCUIT INCLUDING MULTIPLE MEMORY DEVICES - An integrated circuit includes a data bus and a first memory device coupled to the data bus. The first memory device is configured to provide a first signal in response to completing a power-up sequence of the first memory device. The integrated circuit includes a second memory device coupled to the data bus. The second memory device is configured to provide a second signal in response to completing a power-up sequence of the second memory device. The integrated circuit includes a controller configured to access the first memory device and the second memory device based on the first signal and the second signal. | 01-29-2009 |
| 20090079055 | METHOD AND STRUCTURE OF EXPANDING, UPGRADING, OR FIXING MULTI-CHIP PACKAGE - Embodiments of the present invention generally provide techniques and apparatus for altering the functionality of a multi-chip package (MCP) without requiring entire replacement of the MCP. The MCP may be designed with a top package substrate designed to interface with an add-on package that, when sensed by the MCP, alters the functionality of the MCP. | 03-26-2009 |
| 20090080279 | STRUCTURE TO SHARE INTERNALLY GENERATED VOLTAGES BETWEEN CHIPS IN MCP - Embodiments of the invention generally provide an apparatus and technique for sharing an internally generated voltage between devices of a multi-chip package (MCP). The internally generated voltage may be shared via a conductive structure that electrically couples the devices and carries the internally generated voltage. | 03-26-2009 |
| 20090113078 | METHOD AND APPARATUS FOR IMPLEMENTING MEMORY ENABLED SYSTEMS USING MASTER-SLAVE ARCHITECTURE - Embodiments of the invention generally provide a system, method, and memory device for accessing memory. In one embodiment, a first memory device includes command decoding logic configured to decode commands issued to the first memory device and a second memory device, while command decoding logic of the second memory device is bypassed. | 04-30-2009 |
| 20090113158 | METHOD AND APPARATUS FOR SYNCHRONIZING MEMORY ENABLED SYSTEMS WITH MASTER-SLAVE ARCHITECTURE - Embodiments of the invention generally provide a system, method and memory device for accessing memory. One embodiment includes synchronization circuitry configured to determine timing skew between a first memory device and a second memory device, and introduce a delta delay to at least one of the first memory device and the second memory device to adjust the timing skew. | 04-30-2009 |
| 20090129186 | SELF-DIAGNOSTIC SCHEME FOR DETECTING ERRORS - The present invention is generally related to integrated circuit devices, and more particularly, to methods and systems of a multi-chip package (MCP) containing a self-diagnostic scheme for detecting errors in the MCP. The MCP generally comprises a controller, at least one volatile memory chip having error detection logic, at least one non-volatile memory chip, and at least one fail signature register for storing fail signature data related to memory errors detected in the MCP. The controller can poll the fail signature register for fail signature data related to memory errors stored therein. Upon detection of fail signature data, the controller can store the fail signature data on a fail signature register located on a non-volatile memory. | 05-21-2009 |
| 20090196116 | SEMICONDUCTOR MEMORY HAVING A BANK WITH SUB-BANKS - Methods and apparatus that provide an additional level(s) of hierarchy within a bank of a Dynamic Random Access Memory (DRAM) are provided. The bank has a plurality of separately addressable sub-banks. | 08-06-2009 |
| 20090200652 | METHOD FOR STACKING CHIPS IN A MULTI-CHIP PACKAGE - A multi-chip package is provided that has at least a first, second and third chip, each comprising a top and bottom surface. The multi-chip package also has a package substrate for interfacing with a printed circuit board (PCB). The chips and the package substrate are housed within an encapsulation material. The bottom surface of the first chip is attached to the package substrate. The top surface of the first chip has a first plurality of landing pads, which serve as a mechanical and electrical interface between the first and second chip. The bottom surface of the second chip has a second plurality of landing pads that serve as a mechanical and electrical interface between the second and first chip. Additionally, the top surface of the second chip has a third plurality of landing pads that serve as a mechanical and electrical interface between the second and third chip. | 08-13-2009 |
| 20100124130 | Method and Apparatus to Reduce Power Consumption by Transferring Functionality from Memory Components to a Memory Interface - A common Delay Locked Loop (DLL) circuit and/or voltage generator circuit is provided in, or associated with. a memory interface interposed between a memory controller and a plurality of memory components. Corresponding circuits in the memory components are disabled and/or bypassed, or the memory components are manufactured without the circuits. Both the DLL circuit and voltage generator draw current, which is multiplied by the number of memory components in a memory system. By operating a single DLL circuit and/or voltage generator in or associated with the memory interface, that generates a read clock signal and/or various voltage levels, respectively, for all memory components in the memory system, power consumption may be significantly reduced. | 05-20-2010 |
