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Jong-Hoon
Jong Hoon Kang, Seoul KR
| Patent application number | Description | Published |
|---|---|---|
| 20090315069 | THIN GALLIUM NITRIDE LIGHT EMITTING DIODE DEVICE - Disclosed is a light emitting diode (LED) device that comprises a crystal structure of a sapphire substrate-free gallium nitride (GaN) LED, wherein the crystal structure is mounted on a first surface of a sub-mount substrate in the form of a unit chip, and the first surface of the sub-mount substrate has a surface area greater than the surface area of a region in which the unit chip is bonded. Preforms for manufacturing the LED device and a method for manufacturing the LED device are also disclosed. The sapphire substrate, on which the crystal structure of the light emitting diode has grown, is processed into a unit chip before being removed. Thus, any crack in the crystal structure of the light emitting diode that may occur during the removal of the sapphire substrate can be prevented. Therefore, a thin light emitting diode device can be manufactured in a mass production system. | 12-24-2009 |
Jong Hoon Kim, Suwon-Si KR
| Patent application number | Description | Published |
|---|---|---|
| 20110309358 | SEMICONDUCTOR CHIP WITH FINE PITCH LEADS FOR NORMAL TESTING OF SAME - A semiconductor chip includes a semiconductor substrate having a top surface and a bottom surface. A circuit layer having bonding pads may be formed over the top surface of the semiconductor substrate. Through electrodes may be formed to pass from a bottom surface to a top surface of the semiconductor substrate, and the through electrodes may comprise through parts connected with the bonding pads and projecting parts formed over the bottom surface of the semiconductor substrate and electrically connected with the through parts. Test pad parts may be disposed over the bottom surface of the semiconductor substrate and is connected with the through electrodes to test normal operation of the circuit layer and electrical connections of the through electrodes and the circuit layer. | 12-22-2011 |
Jong Hoon Kim, Seongnam-Si KR
| Patent application number | Description | Published |
|---|---|---|
| 20080231821 | Exposure Method Of A Semiconductor Device - An exposure method of a semiconductor device includes the steps of: providing a wafer on which a photoresist is coated; rotating and aligning a reticle and the wafer so that a swing direction of a light source passing through the reticle is identical to a direction of a word line formed on the wafer; and performing an exposure process employing a polarized light source of an X direction, the polarized light source being generated by passing the light source through a dipole X-illumination system | 09-25-2008 |
Jong Hoon Oh, Seoul KR
| Patent application number | Description | Published |
|---|---|---|
| 20110054915 | COMPUTING CIRCUITS AND METHOD FOR RUNNING AN MPEG-2 AAC OR MPEG-4 AAC AUDIO DECODING ALGORITHM ON PROGRAMMABLE PROCESSORS - The present invention relates to computing circuits and method for running an MPEG-2 AAC or MPEG-4 AAC algorithm efficiently, which is used as an audio compression algorithm in multi-channel high-quality audio systems, on programmable processors. In accordance with the present invention, the IMDCT process which takes large part of the amount of the operations in implementation of an MPEG-2/4 AAC algorithm can be performed in efficient. In addition, while the architecture of the existing digital signal processor is still used, the performance can be improved by means of the addition of the architecture of the address generator, Huffman decoder, and bit processing architecture. After all, to design and change the programmable processor is facilitated. | 03-03-2011 |
Jong Hoon Park, Gyeonggi-Do KR
| Patent application number | Description | Published |
|---|---|---|
| 20110220727 | RFID Tag Antenna and RFID Tag - The present invention relates to a radio frequency identification (RFID) tag antenna and an RFID tag, in which a connection part where a radiator dipole and a T-junction are connected has a branch structure, so that an electric current can be induced in the T-junction and the radiator dipole by the branch structure, and the amount of the electric current induced in the radiator dipole can be adjusted to thereby control impedance of the RFID tag antenna in detail. The RFID tag antenna includes: a substrate; a radiator dipole symmetrically printed on the substrate in a form of meanders; and a T-junction formed between the symmetrical radiator dipoles, formed integrally with each end part of the symmetrical radiator dipoles and performing impedance matching between the radiator dipole and an RFID tag chip, wherein a connection part where the symmetrical radiator dipole and the T-junction are connected has a branch structure. | 09-15-2011 |
Jong-Hoon Chung, Gunpo-Si KR
| Patent application number | Description | Published |
|---|---|---|
| 20100005166 | NETWORK DEVICE - The present invention discloses a network device which can access a home network system and perform network communication based on a predetermined protocol, by using a minimum number of resources of an embedded microcontroller The network device communicates with at least one electric device through a network. The network device adopts a protocol consisting of an application layer for processing a message for controlling or monitoring the electric device, a network layer for performing network connection to the electric device, a data link layer for accessing a shared transmission medium, and a physical layer for providing a physical interface with the electric device. The application layer further includes an application sublayer for performing a network management function or managing device information. | 01-07-2010 |
Jong-Hoon Jung, Suwon-Si KR
| Patent application number | Description | Published |
|---|---|---|
| 20090310339 | BACKLIGHT UNIT FOR LIQUID CRYSTAL DISPLAY DEVICE - Provided is a backlight unit for a liquid crystal display device. The backlight unit includes: a chassis; a printed circuit board connected to a side of the chassis, the printed circuit board including a plurality of light emitting diodes, and a pair of conductive pads through which power is supplied to the light emitting diodes, wherein the pair of conductive pads are disposed on an end of the printed circuit board; and a power socket into which the pair of the conductive pads are inserted. | 12-17-2009 |
| 20110057965 | LIQUID CRYSTAL DISPLAY DEVICE INCLUDING EDGE-TYPE BACKLIGHT UNIT AND METHOD OF CONTROLLING THE LIQUID CRYSTAL DISPLAY - A method of controlling a liquid crystal display (LCD) device including an LCD panel and an edge-type backlight unit is provided. The method includes: controlling turn-on and turn-off periods of an upper light source unit and a lower light source unit of the edge-type backlight unit to be synchronized with a period during which a 3D image is output on the LCD panel, wherein the upper light source unit includes a light source disposed at an upper edge of the edge-type backlight unit, and the lower light source unit includes a light source disposed at a lower edge of the edge-type backlight unit. | 03-10-2011 |
| 20110096105 | METHOD AND APPARATUS FOR COMPENSATING FOR TEMPERATURE VARIATIONS OF A LIQUID CRYSTAL DISPLAY PANEL FOR A 3-DIMENSIONAL DISPLAY - Methods and apparatuses are provided for compensating for a temperature of a liquid crystal display (LCD) panel. The method includes selecting a lookup table corresponding to a detected temperature of the LCD panel from among lookup tables for a 3-dimensional (3D) display of the LCD panel; and adjusting luminance to be output to the LCD panel based on the selected lookup table. | 04-28-2011 |
| 20110102422 | TWO-DIMENSIONAL/THREE-DIMENSIONAL IMAGE DISPLAY APPARATUS AND METHOD OF DRIVING THE SAME - A display apparatus which displays two-dimensional (2D) and three-dimensional (3D) images and a method of driving the same. In the 2D/3D image display apparatus, an image signal input unit inputs, to a display panel, a left image signal, a left inversion image signal, at least one 2D image signal, a right image signal and a right inversion image signal, a left shutter of shutter glasses is open in synchronization with the left image signal, a right shutter of the shutter glasses is open in synchronization with the right image signal, and the left shutter and the right shutter of the shutter glasses are closed in synchronization with the left inversion image signal, the at least one 2D image signal, and the right inversion image signal. | 05-05-2011 |
| 20110148863 | 3D DISPLAY DRIVING METHOD AND 3D DISPLAY APPARATUS USING THE SAME - A method for driving a 3D display and a display apparatus using the same are provided. The display apparatus includes a storage unit to store a received image and a controlling unit to drive a display by adjusting the brightness value using a first look-up table when the previous frame is different from the current frame and adjusting the brightness value using a second look-up table when the previous frame is the same as the current frame. According to the exemplary embodiment, an overdrive method may be applied to a 3D image display apparatus effectively. | 06-23-2011 |
| 20110148943 | METHOD FOR DRIVING THREE-DIMENSIONAL (3D) DISPLAY AND 3D DISPLAY APPARATUS USING THE SAME - A method for driving a three dimensional (3D) display and a 3D display apparatus using the same are provided. The 3D display apparatus includes a storage unit which stores a received image; and a controller which compares a previous frame of the received image with a current frame of the received image, and determines whether or not to input an image of the current frame to a liquid crystal panel based on whether the previous frame is identical to the current frame. Therefore, a method for driving a 3D display which does not cause characteristics of a liquid crystal to be deteriorated and a 3D display apparatus using the same are provided. | 06-23-2011 |
| 20110157165 | METHOD AND APPARATUS FOR DISPLAYING 3-DIMENSIONAL IMAGE AND METHOD AND APPARATUS FOR CONTROLLING SHUTTER GLASSES - An image display method includes alternately receiving left and right images of a 3D image; and turning on a backlight such that the backlight is on only in periods when the left images are displayed or only in periods when the right images are displayed. A method of controlling shutter glasses separately for left and right images of a three-dimensional (3D) image includes alternately receiving the left and right images of the 3D image; and opening two shutters of the shutter glasses only in periods when the left images are received or only in periods when the right images are received. | 06-30-2011 |
| 20110193897 | METHOD AND APPARATUS FOR CONTROLLING THE PARTITIONS OF A BACKLIGHT UNIT OF A 3D DISPLAY APPARATUS - A method and apparatus for controlling a backlight unit of a three-dimensional (3D) display apparatus receiving a 3D video sequence is provided. The method includes determining the image brightness level of the 3D video sequence displayed on a liquid crystal display (LCD) unit, for each of a plurality of partial regions of the LCD unit to which a plurality of sub-blocks of the backlight unit emit light; determining turn-on times of the plurality of sub-blocks of the backlight unit, based on the image brightness of each of the partial regions of the LCD unit; and determining turn-on periods of the plurality of sub-blocks of the backlight unit by synchronizing with a switching period between a set including a left visual point frame and a right visual point frame of the 3D video sequence. | 08-11-2011 |
| 20110267341 | STEREOSCOPIC DISPLAY APPARATUS AND METHOD OF DRIVING THE SAME - A stereoscopic display apparatus includes a display panel which scans an image at a frame frequency that is an odd-numbered multiple of a field frequency, an image signal input unit which inputs an image signal to the display panel, a backlight unit which emits light to the display panel, and a shutter controller which controls an opening and a closing of a left eye shutter and a right eye shutter of shutter glasses. | 11-03-2011 |
| 20110292041 | STEREOSCOPIC DISPLAY APPARATUS AND METHOD OF DRIVING THE SAME - A stereoscopic display apparatus is provided. The display apparatus includes a display panel for scanning an image alternately at a first frame frequency and a second frame frequency, different from the first frame frequency, an image signal input unit for inputting an image signal to the display panel, a backlight unit for emitting light to the display panel, and a shutter controller for selectively controlling an opening and closing of a left eye shutter and a right eye shutter of shutter glasses. | 12-01-2011 |
| 20120086712 | 3D DISPLAY PANEL AND 3D DISPLAY APPARATUS USING THE SAME AND DRIVING METHOD THEREOF - A three-dimensional (3D) display panel, a 3D display apparatus using the same, and a driving method thereof are provided. The 3D display apparatus includes: an image display panel which displays an image; a phase shift panel which alternately shifts a polarization direction of light outputted from the image display panel; a backlight unit which provides a backlight; and a control unit which turns off the backlight unit during a crosstalk period where the phase shift panel performs the shift operation and to turn on the backlight unit for a stabilization period after the crosstalk period. | 04-12-2012 |
Jong-Hoon Jung, Seoul KR
| Patent application number | Description | Published |
|---|---|---|
| 20080310243 | Semiconductor memory device for reducing precharge time - A semiconductor memory device for reducing a precharge time is provided. The semiconductor memory device may include a sense amplifier, a precharge unit and an equalizing circuit. The sense amplifier may sense and amplify a difference between data transmitted through a first bit line and data transmitted through a second bit line in response to a sense amplifier enable signal. The precharge unit may precharge voltage levels of the first bit line and the second bit line to a precharge voltage level in response to a precharge enable signal. The equalizing circuit may be connected to the sense amplifier and the precharge unit and may control the voltage levels of the first bit line and the second bit line to be equal to each other in response to the sense amplifier enable signal. The semiconductor memory device may reduce a time required to perform a precharge operation and/or minimize an increase of the circuit size. | 12-18-2008 |
| 20090034348 | WRITE DRIVER CIRCUIT OF AN UNMUXED BIT LINE SCHEME - A write driver circuit of a semiconductor memory to provide an unmuxed bit line scheme which reduces a height of an unmuxed Y-path so as to reduce an area of a chip in the memory. The write driver circuit can include an input latch circuit which latches input data, in response to an input enable signal; a first write driver which receives write data output from the input latch circuit, in response to a write enable signal, and outputs data to a bit line; and a second write driver which receives inverse data of the write data output from the input latch circuit, in response to the write enable signal, and outputs data to a complementary bit line, wherein the first and second write drivers have a NAND gate type structure and function as a write driver and a precharge driver. | 02-05-2009 |
| 20090251984 | Static memory device and static random access memory device - A static memory device includes a bit cell connected to an internal voltage line, and a power supply control circuit connected between the internal voltage line and a power supply voltage, wherein the power supply control circuit is configured to supply the power supply voltage level to the internal voltage line, and the power supply control circuit is configured to perform a write assist function that includes floating the internal voltage line during a write operation on the bit cell, the internal voltage line being floated in response to a signal of a mode control signal group. | 10-08-2009 |
Jong-Hoon Kang, Suwon-Si KR
| Patent application number | Description | Published |
|---|---|---|
| 20090325356 | METHODS OF FORMING A LOW TEMPERATURE DEPOSITION LAYER AND METHODS OF MANUFACTURING SEMICONDUCTOR DEVICE USING THE SAME - Provided are methods of forming a low temperature deposition layer and methods of manufacturing a semiconductor device using the same. The method of manufacturing a semiconductor device comprises forming a mask layer exposing a gate pattern on a substrate on which the gate pattern is formed, forming a sacrifice layer on the mask layer and on a substrate not covered by the mask layer using a plasma ion immersion implantation and deposition (PIIID), and doping a substrate adjacent to both sidewalls of the gate pattern with an impurity. | 12-31-2009 |
| 20100109057 | Fin field effect transistor and method of fabricating the same - A fin field effect transistor includes a fin protruding from a semiconductor substrate, a gate insulating layer formed so as to cover upper and lateral surfaces of the fin, and a gate electrode formed across the fin so as to cover the gate insulating layer. An upper edge of the fin is rounded so that an electric field concentratedly applied to the upper edge of the fin through the gate electrode is dispersed. A thickness of a portion of the gate insulating layer formed on an upper surface of the fin is greater than a thickness of a portion of the gate insulating layer formed on a lateral surface of the fin, in order to reduce an electric field applied through the gate electrode. | 05-06-2010 |
| 20110237037 | Methods of Forming Recessed Channel Array Transistors and Methods of Manufacturing Semiconductor Devices - In methods of manufacturing a recessed channel array transistor, a recess may be formed in an active region of a substrate. A plasma oxidation process may be performed on the substrate to form a preliminary gate oxide layer on an inner surface of the recess and an upper surface of the substrate. Moistures may be absorbed in a surface of the preliminary gate oxide layer to form a gate oxide layer. A gate electrode may be formed on the gate oxide layer to fill up the recess. Source/drain regions may be formed in an upper surface of the substrate at both sides of the gate electrode. Thus, the oxide layer may have a uniform thickness distribution and a dense structure. | 09-29-2011 |
Jong-Hoon Kang, Gyeonggi-Do KR
| Patent application number | Description | Published |
|---|---|---|
| 20090068823 | Plasma Ion Doping Method and Apparatus - In plasma ion doping operations, a wafer is positioned on a susceptor within a reaction chamber and an ion doping source gas is plasmalyzed in an upper part of the reaction chamber above a major surface of the wafer while supplying a control gas into the reaction chamber in a lower part of the reaction chamber opposite the major surface of the wafer to thereby dope ions into the major surface of the wafer. The ion doping source gas may comprise at least one halide gas, and the control gas may comprise at least one depositing gas, such as a silane gas. In further embodiments, a diluent gas, such as an inert gas, may be supplied to the reaction chamber while supplying the ion doping source gas and the control gas. Related plasma ion doping apparatus are described. | 03-12-2009 |
| 20100025749 | SEMICONDUCTOR DEVICE - A semiconductor device may include an isolation layer, gate electrodes, an insulating interlayer, an impurity region, a capping layer and a plug. The isolation layer may be formed in the substrate. The gate electrodes may be formed on the substrate. The insulating interlayer may be formed on the gate electrodes. The insulating interlayer may have a contact hole between the gate electrodes. The impurity region may be in the substrate exposed through the contact hole. The capping layer may be on the impurity region. The plug may be on the capping layer. Thus, the impurities may not be lost from the impurity region. As a result, the device may have improved electrical characteristics and reliability because depletion may not be generated in the electrode layer | 02-04-2010 |
| 20100035425 | Integrated Circuit Devices Having Partially Nitridated Sidewalls and Devices Formed Thereby - Methods of forming integrated circuit devices include forming an electrically conductive layer containing silicon on a substrate and forming a mask pattern on the electrically conductive layer. The electrically conductive layer is selectively etched to define a first sidewall thereon, using the mask pattern as an etching mask. The first sidewall of the electrically conductive layer may be exposed to a nitrogen plasma to thereby form a first silicon nitride layer on the first sidewall. The electrically conductive layer is then selectively etched again to expose a second sidewall thereon that is free of the first silicon nitride layer. The mask pattern may be used again as an etching mask during this second step of selectively etching the electrically conductive layer. | 02-11-2010 |
| 20100072545 | Recessed Channel Array Transistors, and Semiconductor Devices Including a Recessed Channel Array Transistor - A recessed channel array transistor may include a substrate, a gate oxide layer, a gate electrode and source/drain regions. The substrate may have an active region and an isolation region. A recess may be formed in the active region. The gate oxide layer may be formed on the recess and the substrate. The gate oxide layer may include a first portion on an intersection between a side end of the recess and a sidewall of the active region and a second portion on a side surface of the recess. The first portion may include a thickness greater than about 70% of a thickness of the second portion. The gate electrode may be formed on the gate oxide layer. The source/drain regions may be formed in the substrate. Thus, the recessed channel array transistor may have a decreased leakage current and an increased on-current. | 03-25-2010 |
Jong-Hoon Lee, Daegu KR
| Patent application number | Description | Published |
|---|---|---|
| 20100290782 | REMOTE NODE CONFIGURATION FOR PROVIDING UPGRADED SERVICES IN A PASSIVE OPTICAL NETWORK AND A PASSIVE OPTICAL NETWORK HAVING THE SAME - The present invention discloses a remote node (RN) configuration for providing an enhanced service in a passive optical network and a passive optical network (PON) having the same. In an RN configuration for providing a new service in a PON according to the present invention, it is possible to configure the RN remotely by instantaneous powering from a remote site only when necessary, while the RN being operated as a PON at ordinary times. More specifically, an RN configuration for providing a new service in a PON according to the present invention includes a power generation block capable of providing energy necessary for activating the RN by instantaneously supplied power from the remote site. Further, an RN according to the present invention further includes either one or both of a control agent block capable of controlling and managing optical paths of the RN by using power generated from the power generation block; and a reconfigurable switching block capable of configuring and switching the optical path of the RN through the power being provided from the power generation block and a control by the control agent block. | 11-18-2010 |
| 20110255860 | FAULT LOCALIZATION METHOD AND A FAULT LOCALIZATION APPARATUS IN A PASSIVE OPTICAL NETWORK AND A PASSIVE OPTICAL NETWORK HAVING THE SAME - The present invention discloses a fault localization method and a fault localization apparatus in a Passive Optical Network (PON) and a passive optical network having the same. | 10-20-2011 |
Jong-Hoon Lee, Daejeon-Si KR
| Patent application number | Description | Published |
|---|---|---|
| 20120128360 | OPEN OPTICAL ACCESS NETWORK SYSTEM - The present invention relates to an open optical access network system in which one optical access network is open to enable a plurality of service providers and a plurality of subscribers to simultaneously use the optical access network, to thereby improve the efficiency of using the optical access network, wherein each subscriber can be provided with a plurality of different services from the plurality of service providers, thereby enabling the flexible selection of services and the flexible change in services, thus improving the efficiency of using an optical infrastructure. | 05-24-2012 |
Jong-Hoon Lee, Suwon-Si KR
| Patent application number | Description | Published |
|---|---|---|
| 20090273983 | NONVOLATILE MEMORY DEVICE AND PROGRAMMING METHOD - Disclosed is a programming method for a nonvolatile memory device. The method includes; charging word-line signal lines to a pass voltage during a pass voltage charge operation, simultaneously executing an initial precharge operation for strings including program-inhibited cells during the pass voltage charge operation, and applying the pass voltage to word lines from the word-line signal lines in response to a block-selection enabling signal | 11-05-2009 |
Jong-Hoon Lee, Hwasung-Shi KR
| Patent application number | Description | Published |
|---|---|---|
| 20120084965 | TRANSMISSION MOUNT TYPE OF SIDE ASSEMBLING - A transmission mount type of side assembling includes a cylindrical insulator; a core having a plurality of longitudinal holes and inserted in the insulator; a side stopper having a support connected to one end of the core in contact with the inner side of the insulator and a protrusion protruding outside the insulator from the support; a cylindrical case accommodating the core, the side stopper, and the insulator; and a plurality of bolts that is longer than the case and inserted through holes in the core and the side stopper from a side to protrude outside the case, such that it can simplify the assembly process of fastening a transmission to a car body and reduce the manufacturing cost, without changing the existing manufacturing line, and ensure safety in assembly. | 04-12-2012 |
Jong-Hoon Lee, Yongin-Si KR
| Patent application number | Description | Published |
|---|---|---|
| 20090092016 | Optical recording/reproducing write strategy method, medium, and apparatus - A write strategy method, medium, and apparatus. The method includes writing a signal to a storage medium by using a predetermined power and an initial write strategy, calculating variation characteristics of a data signal which separately correspond to variations of write strategy parameters, if the written signal does not satisfy initial quality standards, and calculating correlations among periods of the data signal and correlations among the write strategy parameters by using the variation characteristics of the data signal, and determining the write strategy parameters based on the correlations among the periods of the data signal and the correlations among the write strategy parameters. | 04-09-2009 |
| 20110187662 | MOBILE DEVICE WITH DUAL DISPLAY UNITS AND METHOD FOR CONTROLLING THE DUAL DISPLAY UNITS - A mobile device with dual display units and a method for displaying screen images are provided. The two display units cooperate to serve as one combined display device and display one screen image thereon. Alternatively, the two display units can be independently operated and can display different screen images thereon, respectively. The method includes displaying screen images according to an execution of a particular mode on at least one of first and second display units, and displaying a screen image, searched for according to an execution of a search function, on at least one of the first and second display units, based on whether a dual mode is selected. | 08-04-2011 |
Jong-Hoon Lee, Hwaseong-Si KR
| Patent application number | Description | Published |
|---|---|---|
| 20110305087 | FLASH MEMORY DEVICE AND READING METHOD THEREOF - A flash memory device wherein off cell margin is increased by controlling a voltage of a sensing node and a corresponding reading method, wherein the flash memory device includes a memory cell array; a sensing node voltage controller generating a precharge voltage and a sensing node voltage control signal; and a page buffer unit connected to the memory cell array through bit lines and having page buffers. The page buffers include a bit line connection unit connected between a corresponding bit line and a sensing node, that controls a voltage of the sensing node according to the sensing node voltage control signal; a precharge unit which precharges the sensing node according to the precharge voltage responsive to a precharge control signal; and a data input/output unit sensing a voltage level of the sensing node responsive to a latch control signal and outputting the data of the selected memory cell. | 12-15-2011 |
| 20120020167 | FLASH MEMORY DEVICE AND A METHOD OF PROGRAMMING THE SAME - A flash memory device includes a memory cell array including a plurality of memory cells; a bit line voltage control signal generator generating and outputting a bit line voltage control signal; and a page buffer unit connected to the memory cell array through a plurality of bit lines, and controlling voltage levels of the plurality of bit lines in response to the bit line voltage control signal output from the bit line voltage control signal generator, wherein the plurality of bit lines comprise a first bit line and a second bit line adjacent to the first bit line, wherein during a bit line pre-charging operation in which the first bit line is in a program inhibited state and the second bit line is in a programming state, the page buffer unit increases a voltage level of the first bit line in response to the bit line voltage control signal, wherein the increase in the voltage level of the first bit line causes a voltage level of the second bit line to increase, and wherein a voltage level of the bit line voltage control signal is not affected by a change in a power voltage of the flash memory device. | 01-26-2012 |
Jong-Hoon Lim, Seoul KR
| Patent application number | Description | Published |
|---|---|---|
| 20100160617 | NUCLEASE-RESISTANT RNA APTAMER INHIBITING REPLICATION OF HEPATITIS C VIRUS REPLICON - Disclosed a nuclease-resistant RNA aptamer for inhibiting the replication of HCV replicon. This aptamer is capable of binding specifically to HCV NS5B and inhibiting the proliferation of the HCV replicon, and is composed of at least one sequence selected from a group consisting of SEQ ID NOS. 1 to 4, in which a fluoro group is substituted for 2′-hydroxy of both U (uracil) and C (cytosine) bases, and SEQ ID NO. 4, which is tagged with a cholesteryl group at a 5′ end and with idT at a 3′ end. The RNA aptamer is useful in the diagnosis and treatment of HCV infection. | 06-24-2010 |
Jong-Hoon Lim, Suwon-Si KR
| Patent application number | Description | Published |
|---|---|---|
| 20090072699 | CATHODE RAY TUBE WITH IMPROVED MASK ASSEMBLY - A cathode ray tube including a shadow mask. The shadow mask includes an aperture portion including a plurality of beam guide holes, a non-aperture portion surrounding the aperture portion, and a skirt portion that is bent from an edge of the non-aperture portion toward an electron gun. The non-aperture portion includes a pair of longer sides, a pair of shorter sides, and four corner portions, and a first width of the non-aperture portion measured at the longer side and a second width of the non-aperture portion measured at the shorter side are formed to be less than a third width of the non-aperture portion measured at the corner portions. The shadow mask satisfies the following conditions: 2 mm≦w | 03-19-2009 |
Jong-Hoon Park, Seoul KR
| Patent application number | Description | Published |
|---|---|---|
| 20090162865 | BREAST CANCER RELATED PROTEIN, GENE ENCODING THE SAME, AND METHOD OF DIAGNOSING BREAST CANCER USING THE PROTEIN AND GENE - An isolated protein having an amino acid sequence of SEQ ID No. 4 and having an activity inducing apoptosis, and a gene encoding the same are provided. Also, a microarray having a substrate on which the gene or fragment thereof is immobilized is provided. Also, a method of diagnosing breast cancer using an antibody specifically binding to the protein and a method of diagnosing breast cancer by determining whether the gene is expressed in a cell or not, are provided. | 06-25-2009 |
| 20100281553 | PRODUCTION METHOD OF CYST EXPRESSED TRANSGENIC ANIMAL USING PKD2 GENE - Disclosed herein is a method for producing a cyst-expressed transgenic animal using a PDK2 gene. The production method comprises preparing a PKD2 protein expression vector, inserting the expression vector into the nucleus of a fertilized egg to produce a PKD2 expression vector-containing fertilized egg, and transplanting the produced fertilized egg into the uterus of a surrogate mother. According to the invention disclosed herein, there is provided a method for producing transgenic animals, in which cysts are expressed only by the overexpression of the PKD2 gene. Also, transgenic mice are provided which can be effectively used in the investigation of cyst expression mechanisms and cyst control systems. | 11-04-2010 |
Jong-Hoon Shin, Suwon-Si KR
| Patent application number | Description | Published |
|---|---|---|
| 20090129062 | LIGHT EMISSION DEVICE AND DISPLAY DEVICE USING THE LIGHT EMISSION DEVICE AS ITS LIGHT SOURCE - A light emission device capable of enhancing its luminance and durability and a display device utilizing the light emission device as a light source. The light emission device includes first and second substrates facing each other, cathode electrodes arranged on the first substrate and extending in a first direction, gate electrodes arranged above the cathode electrodes and extending in a second direction crossing the first direction, a plurality of electron emission regions electrically coupled to the cathode electrodes, and a light emission unit provided on the second substrate and including an anode electrode and a phosphor layer. The first substrate has an active area and a non-active area surrounding the active area, and a total area of the electron emission regions on the first substrate is between about 2 and about 26% of the active area. | 05-21-2009 |
| 20090200368 | Method of Multi-Interfacing Between Smart Card and Memory Card, and Multi-Interface Card - A multi-interface card includes smart card interface, memory card interface, card controller and memory module. The smart card interface interfaces with a smart card host using a smart card protocol. The memory card interface interfaces with a memory card host using a memory card protocol. The card controller controls the smart card host and memory card host so that the smart card host and the memory card host simultaneously interface with the smart card and the memory card interfaces, respectively. The memory module stores data transferred from the smart card host and memory card host. The multi-interface card simultaneously supports the smart card interface and the memory card interface. Thus, the one multi-interface card can support a subscriber authentication function and a data storage function. | 08-13-2009 |
Jong-Hoon Woo, Bucheon KR
| Patent application number | Description | Published |
|---|---|---|
| 20090015763 | LIQUID CRYSTAL DISPLAY DEVICE AND METHOD OF FABRICATING THE SAME - A liquid crystal display (LCD) device comprises a substrate, and red, green, blue (RGB) color filters. The RGB color filters are spaced from one another with a predetermined gap therebetween on the substrate, and define RGB sub-pixels. The LCD device further comprises black matrixes disposed at each space between the RGB color filters, and barriers disposed at each interface among the RGB sub-pixels such that the barriers control a path of light that passes through a corresponding sub-pixel. | 01-15-2009 |
Jong-Hoon Woo, Bucheon-Si KR
| Patent application number | Description | Published |
|---|---|---|
| 20080316398 | Liquid crystal display device - A liquid crystal display device, in which a plurality of pixels are defined in a matrix form and each pixel includes red, green, blue, and white sub-pixels adjacent to one another vertically and horizontally, is disclosed. The liquid crystal display device includes first, second, and third substrates sequentially stacked from the bottom, a thin-film transistor array formed on the first substrate, a black matrix formed on the second substrate between the first substrate and the second substrate at the boundary of the respective sub-pixels, a color filter layer formed on the second substrate between the first substrate and the second substrate at the respective sub-pixels, and a barrier layer formed on the third substrate over each white sub-pixel. An opening in the white sub-pixel has a smaller size than that of openings in the red, green, and blue sub-pixels. Also, an angle defined between a normal line of the second substrate and a line that connects an edge of the barrier layer with an edge of the black matrix formed below the barrier layer is larger than a value calculated by subtracting 5 degrees from an angle causing the total reflection of light to be passed through the second substrate. | 12-25-2008 |
| 20090140950 | Display device having multiple viewing zones and method of displaying multiple images - A display device having multiple viewing zones includes a display panel including a plurality of pixels in a matrix form, each pixel including red, green and blue sub-pixels arranged in a vertical direction; and a light guide panel guiding a first image emitted from the pixels in first columns among the plurality of pixels to a first viewing zone and a second image emitted from the pixels in second columns among the plurality of pixels to a second viewing zone, wherein the first column is adjacent to the second column. | 06-04-2009 |