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Jong-Han
Jong Han Beock, Gumi-Si KR
| Patent application number | Description | Published |
|---|---|---|
| 20080198141 | Touch event-driven display control system and method for touchscreen mobile phone - A touch event-driven display control system and method for a touchscreen mobile phone is provided to control the information display by onscreen touch manipulation. An information display method for a touchscreen-enabled device according to the present invention includes detecting a touch on an information region of a touchscreen, determining a type of the touch and processing display of information item according to the type of touch. | 08-21-2008 |
| 20080215980 | User interface providing method for mobile terminal having touch screen - A user interface providing method and apparatus for a mobile terminal is disclosed. A managing area and a touch action area are set on a touch screen. A desired data file in the managing area is dragged and dropped into the touch action area, thereby playing the data file. The user can play a particular data file through simple drag and drop actions. As a result, the user can use a desired function of the mobile terminal in an intuitive manner. | 09-04-2008 |
Jong Han Oh, Gyeonggi-Do KR
| Patent application number | Description | Published |
|---|---|---|
| 20090156355 | System and method for controlling clutch engagement in hybrid vehicle - The present invention provides a system and method for controlling clutch engagement in a hybrid vehicle, in which an appropriate clutch engagement mode is selected based on vehicle state, and the like, and a speed difference between both sections of a clutch and a torque transmitted to the vehicle during the clutch engagement process are controlled by reflecting a parameter changed by the clutch engagement mode, thus improving acceleration performance and driving performance, reducing engagement impact, and simply providing various clutch engagement modes. | 06-18-2009 |
Jong Han Oh, Suwon-Si KR
| Patent application number | Description | Published |
|---|---|---|
| 20100119710 | Patterning apparatus and method using dip-pen nanolithography - An apparatus and a method according to example embodiments is capable of patterning ink on a substrate by using dip-pen nanolithography regardless of the interaction between the ink and the substrate. The patterning apparatus may includes a heat supply control device. The heat supply control device may supply heat so as to liquefy the ink and facilitate the patterning of the ink on the substrate. The melting point of the ink may be set within the predetermined temperature controlled by the heat supply control device. | 05-13-2010 |
| 20110122187 | Ink discharge device of inkjet head and control method thereof - Example embodiments are directed to an ink discharge device that discharges uniform amounts of ink droplets from an inkjet head, and a control method thereof. Voltages applied to plural nozzles of the ink-head are changed based on different characteristics of the respective nozzles to discharge uniform amounts of ink droplets from the nozzles. Voltage increments are calculated using a fixed target color value so as to set color value dispersion and voltage increments are calculated using different target color values according to the nozzles so as to satisfy color value differences between the neighboring pixels and thus time required for a DPN process is shortened, and excessive changes of the applied voltages are prevented and thus a preparatory period required to mass-produce an LCD panel is shortened and yield of the LCD panel is increased. | 05-26-2011 |
Jong Han Park, Pasadena, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20100329276 | Energy efficient network forwarding - Includes a method that determines utilization of a link and determines a weight for the link based on an energy metric for the determined utilization. The method also includes transmitting the determined weight to at least one node adjacent in the network to the network forwarding device, and determining forwarding based on the transmitted weight. | 12-30-2010 |
| 20110154080 | METHOD AND APPARATUS FOR I/O DEVICES ASSISTED PLATFORM POWER MANAGEMENT - Embodiments of an apparatus, system and method are described for input/output (I/O) device assisted platform power management. An apparatus may comprise, for example, power management logic operative to receive idle duration information from one or more input/output (I/O) devices and to modify a power state for one or more components based on the idle information. Other embodiments are described and claimed. | 06-23-2011 |
Jong Han Shin, Seoul KR
| Patent application number | Description | Published |
|---|---|---|
| 20090170302 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE HAVING VERTICAL TRANSISTOR - A method for manufacturing a semiconductor device having a vertical transistor includes forming hard masks on a semiconductor substrate to expose portions of the semiconductor substrate. Then the exposed portions of the semiconductor substrate are etched to define grooves in the semiconductor substrate. A gate conductive layer is formed on the hard masks and surfaces of the grooves to a thickness that does not completely fill the grooves. A sacrificial layer is formed on the gate conductive layer to completely fill the grooves. A partial thickness of the sacrificial layer is removed to expose the gate conductive layer and portions of the gate conductive layer formed on the hard masks and on sidewalls of upper portions of the grooves are removed. The remaining sacrificial layer is completely removed. Gates are formed on sidewalls of lower portions of the grooves by etching the gate conductive layer. | 07-02-2009 |
| 20100096691 | SEMICONDUCTOR DEVICE HAVING VERTICALLY ALIGNED PILLAR STRUCTURES THAT HAVE FLAT SIDE SURFACES AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device having vertically aligned transistors made from pillar structures that have flat side surfaces is presented. The semiconductor device includes a semiconductor substrate, spacers, and gates. The semiconductor substrate has lo pillar structures that have flat side surfaces. The spacers are on sidewalls only on the upper portions of the pillar structures. The gates surround lower portions of the pillar structures. | 04-22-2010 |
Jong Han Shin, Ichon KR
| Patent application number | Description | Published |
|---|---|---|
| 20090127653 | PHASE-CHANGE RANDOM ACCESS MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - A method of manufacturing a phase-change random access memory device includes forming an interlayer insulating film on a semiconductor substrate, on which a bottom structure is formed, and patterning the interlayer insulating film to form a contact hole, forming a spacer on the side wall of the contact hole; forming a dielectric layer in the contact hole, and removing the spacer to form a bottom electrode contact hole. Therefore, the contact area between the bottom electrode contact and the phase-change material layer can be minimized. | 05-21-2009 |
Jong-Han Choi, Hwaseong-Si KR
| Patent application number | Description | Published |
|---|---|---|
| 20110187755 | Single-Chip Display-Driving Circuit, Display Device and Display System Having the Same - Display devices include a display driving circuit, which is configured to generate a source driving signal and a gate driving signal in response to image data and horizontal and vertical sync signals. This display driving circuit includes a resolution-type generator, a timing controller, a source driving circuit and a gate driving circuit. The resolution-type generator is configured to generate a resolution-type signal in response to a resolution selecting code and the timing controller is configured to generate first image data, a source driver control signal and a gate driver control signal in response to the resolution-type signal, the image data and the horizontal and vertical sync signals. The source driving circuit is configured to generate the source driving signal in response to grayscale voltages, the first image data and the source driver control signal. The gate driving circuit is configured to generate the gate driving signal in response to the gate driver control signal. | 08-04-2011 |
Jong-Han Jeong, Youngin KR
| Patent application number | Description | Published |
|---|---|---|
| 20110193083 | THIN FILM TRANSISTOR, METHOD OF MANUFACTURING THE SAME AND FLAT PANEL DISPLAY DEVICE HAVING THE SAME - A thin film transistor (TFT) using an oxide semiconductor as an active layer, a method of manufacturing the TFT, and a flat panel display device having the TFT include source and drain electrodes formed on a substrate; an active layer formed of an oxide semiconductor disposed on the source and drain electrodes; a gate electrode; and an interfacial stability layer formed on at least one of top and bottom surfaces of the active layer. In the TFT, the interfacial stability layer is formed of an oxide having a band gap of 3.0 to 8.0eV. Since the interfacial stability layer has the same characteristics as a gate insulating layer and a passivation layer, chemically high interface stability is maintained. Since the interfacial stability layer has a band gap equal to or greater than that of the active layer, charge trapping is physically prevented. | 08-11-2011 |
Jong-Han Jin, Yuseong-Gu KR
| Patent application number | Description | Published |
|---|---|---|
| 20100098118 | LAPTOP-SIZE HIGH-ORDER HARMONIC GENERATION APPARATUS USING NEAR FIELD ENHANCEMENT - Disclosed herein is a laptop-size high-order harmonic generation apparatus using near field enhancement. The laptop-size high-order harmonic generation apparatus using near field enhancement includes a femtosecond laser generator, light transfer means for transferring light output from the femtosecond laser generator, micro patterns formed of metallic thin films and configured to have nano-sized apertures for generating near field enhancement when the light output from the light transfer means passes through the micro patterns, a gas supply unit for supplying inert gas to the light when the light transferred through the light transfer means passes through the micro patterns, and a vacuum chamber for accommodating the micro patterns and the gas supply unit under a vacuum atmosphere. | 04-22-2010 |
Jong-Han Kim, Gyeonsangnam-Do KR
| Patent application number | Description | Published |
|---|---|---|
| 20080234207 | Pharmaceutical Composition for Preventing and Treating Diabetes or Glucose Control Abnormality Comprising Ginsenosides - The present invention relates to a composition for preventing or treating diabetes or blood glucose control abnormality comprising gisenosides Rg3, Rg5, and Rk1 from natural substances; a use of a mixture comprising gisenosides Rg3, Rg5, and Rk1 for the manufacture of a medicament for preventing or treating diabetes or blood glucose control abnormality; or a method for preventing or treating diabetes or blood glucose control abnormality by administering a therapeutically effective amount of mixture comprising gisenosides Rg3, Rg5, and Rk1 to a subject. The present composition can effectively prevent or treat diabetes, blood glucose control abnormality, and complication thereof. | 09-25-2008 |
Jong-Han Kim, Gyeonggi-Do KR
| Patent application number | Description | Published |
|---|---|---|
| 20080268251 | Acrylic Polymer Beads and Sol Composition Containing the Same - Acrylic polymer beads with excellent coating properties and storage stabilities, its preparation method and acrylic sol composition containing thereof are introduced. | 10-30-2008 |
Jong-Han Lee, Seoul KR
Jong-Han Park, Seoul KR
| Patent application number | Description | Published |
|---|---|---|
| 20080278777 | DOUBLE SIDE IMAGE SCANNER - A double side image scanner includes a frame, a two-way roll feeder, a one-way roll feeder and an image sensor. The frame includes a track that has an entrance, a scanning line joined to the entrance and a circuit line joined to the scanning line. The circuit line is designed to return the medium to the scanning line. The circuit line has a junction point where the circuit line meets with the scanning line, an inlet through which the medium comes into the circuit line from the scanning line and an outlet through which the medium goes out of the circuit line toward the scanning line. A driving means mounted to the frame for driving the two-way roll feeder and the one-way roll feeder. The image sensor obtains image data by scanning the front and rear surfaces of the medium. | 11-13-2008 |
Jong-Han Shin, Ichon-Shi KR
| Patent application number | Description | Published |
|---|---|---|
| 20090117739 | METHOD FOR FORMING PATTERN IN SEMICONDUCTOR DEVICE - A method for forming a pattern in a semiconductor device includes forming an etch-target layer over a substrate, wherein the substrate includes a first region having a smaller pattern than the first region, forming a sacrificial layer and a passivation layer over the etch-target layer, etching the passivation layer and the sacrificial layer to form stack structures including a sacrificial pattern and a passivation pattern, forming spacers over sidewalls of the stack structures, forming a mask pattern covering the second region, removing a portion of the passivation pattern in the first region exposed by the mask pattern to expose a portion of the sacrificial pattern in the first region, removing the exposed portion of the sacrificial pattern in the first region, and etching the etch-target layer to form an etch-target pattern using the spacers in the first and second regions and the stack structure formed between the spacers in the second region. | 05-07-2009 |
Jong-Han Shin, Icheon-Si KR
| Patent application number | Description | Published |
|---|---|---|
| 20090124082 | SLURRY FOR POLISHING RUTHENIUM AND METHOD FOR POLISHING USING THE SAME - A slurry for polishing a ruthenium layer comprises distilled water, sodium periodate (NaIO | 05-14-2009 |
Jong-Han Shin, Gyeonggi-Do KR
| Patent application number | Description | Published |
|---|---|---|
| 20100237405 | SEMICONDUCTOR DEVICE WITH VERTICAL TRANSISTOR AND METHOD FOR FABRICATING THE SAME - A semiconductor device with a vertical transistor includes a plurality of active pillars, a plurality of vertical gates surrounding sidewalls of the active pillars; a plurality of word lines having exposed sidewalls whose surfaces are higher than the active pillars and connecting the adjacent vertical gates together, and a plurality of spacers surrounding the exposed sidewalls of the word lines over the vertical gates. | 09-23-2010 |
| 20100330775 | METHOD FOR FABRICATING SEMICONDUCTOR DEVICE WITH BURIED GATE - A method for fabricating a semiconductor device with a buried gate includes: etching a substrate to form a plurality of trenches; forming a plurality of buried gates that fill lower portions of the trenches; forming a plurality of sealing layers that gap-fill upper portions of the trenches and have protrusions higher than a top surface of the substrate; forming an inter-layer insulation layer over the whole surface of the substrate including the sealing layers; and etching the inter-layer insulation layer to form a contact hole that is aligned with a space between the protrusions of the sealing layers. | 12-30-2010 |
| 20110003459 | METHOD FOR FABRICATING BURIED GATE USING PRE LANDING PLUGS - A method for fabricating a semiconductor device is provided, the method includes forming a plug conductive layer over an entire surface of a substrate, etching the plug conductive layer to form landing plugs, etching the substrate between the landing plugs to form a trench, forming a gate insulation layer over a surface of the trench and forming a buried gate partially filling the trench over the gate insulation layer. | 01-06-2011 |
| 20110156262 | SEMICONDUCTOR DEVICE WITH BURIED GATE AND METHOD FOR FABRICATING THE SAME - A method for fabricating a semiconductor device includes forming landing plugs over a substrate, forming a trench by etching the substrate between the landing plugs, forming a buried gate to partially fill the trench, forming a gap-fill layer to gap-fill an upper side of the buried gate, forming protruding portions of the landing plugs, and trimming the protruding portions of the landing plugs. | 06-30-2011 |
| 20110159664 | METHOD FOR FABRICATING SEMICONDUCTOR DEVICE WITH BURIED GATES - A method for fabricating a semiconductor device includes sequentially stacking a pad oxide layer and a hard mask layer over a substrate, forming a device isolation layer over the substrate, forming a capping layer pattern configured to open a first region of the substrate and cover a second region of the substrate, removing the hard mask layer, removing the capping layer pattern, and removing the pad oxide layer. | 06-30-2011 |