| Patent application number | Description | Published |
|---|
| 20090154586 | MIMO RECEIVER, QR DECOMPOSITION AND MULTI-DIMENSIONAL DETECTION USED IN THE MIMO RECEIVER - Provided are a receiver of a Multiple Input Multiple Output (MIMO) system, QR decomposition and multi-dimensional detection used in the receiver. The receiver includes: a QR decomposing unit for performing a QR decomposing operation in cycles 1 to n | 06-18-2009 |
| 20090154587 | MIMO ANTENNA RECEIVING APPARATUS AND RECEIVING METHOD - Provided is a reception apparatus and method of a Multiple Input Multiple Output (MIMO) system that receives a plurality of different data streams in a multiple cell environment. The reception apparatus for receiving a plurality of different data streams in a multiple input multiple output (MIMO) antenna system includes a data stream detector for detecting each data stream by removing interference between the different data streams while maintaining channel information; and a cochannel interference (CCI) remover for removing cochannel interference from each data stream detected in the data stream detector. The present invention can remove cochannel interference and increase channel capacity to thereby acquire both diversity gain and multiplexing gain. | 06-18-2009 |
| 20090154604 | MULTI-DIMENSIONAL DETECTOR FOR RECEIVER OF MIMO SYSTEM - Provided are a multi-dimensional detector for a receiver of an MIMO system and a method thereof. The multi-dimensional detector includes a first symbol detecting unit for calculating symbol distance values using an upper triangular matrix (R) obtained from QR decomposition to detect an m | 06-18-2009 |
| 20090158112 | METHOD FOR PRODUCING PARITY CHECK MATRIX FOR LOW COMPLEXITY AND HIGH SPEED DECODING, AND APPARATUS AND METHOD FOR CODING LOW DENSITY PARITY CHECK CODE USING THE SAME - Provided are a method for producing a parity check matrix for low complexity and high speed decoding, and an apparatus and method for coding a Low Density Parity Check (LDPC) code using the same. The method includes: calculating a cyclic shift value of a subblock to a matrix; and when the calculated cyclic shift values of the subblock are arrayed in the matrix, producing a parity check matrix by arraying the cyclic shift values of the subblock except ‘0 matrix’ without duplication to any one column. | 06-18-2009 |
| 20090158121 | APPARATUS AND METHOD FOR DECODING LDPC CODE BASED ON PROTOTYPE PARITY CHECK MATRIXES - Provided is an apparatus and method for decoding a Low Density Parity Check (LDPC) code based on prototype parity check matrixes. The apparatus, includes: a parity check matrix selecting means for determining multiple prototype parity check matrixes according to a sub-matrix size and a parallelization figure for processing the parity check matrix; a bit input means for receiving a log likelihood probability value for input bit according to the sub-matrix size and the parallelization figure; a check matrix process means for sequentially performing a partial parallel process on the parity check matrix based on the received log likelihood probability value and the determined multiple prototype parity check matrixes; and a bit process means for determining a bit level based on the partial-parallel processed parity check matrix value and recovering the input bit according to the sub-matrix size and the parallelization figure. | 06-18-2009 |
| 20090164540 | APPARATUS AND METHOD FOR UPDATING CHECK NODE OF LOW DENSITY PARITY CHECK CODE - Provided is an apparatus and method for updating a check node of a LDPC code at a high speed. The apparatus includes: a minimum value calculating unit for calculating a first minimum value of an input bit by sequentially calculating each bit of the first minimum value, and calculating a second minimum value using the calculated first minimum value; a node minimum value calculating unit for performing row splitting the calculated first and second minimum values by a check node and calculating a first minimum value and a second minimum value of each of the row-split nodes; and a minimum value deciding unit for deciding one of the calculated first and second minimum values of each of the row-split nodes as a minimum value corresponding to each degree of the input bit. | 06-25-2009 |
| 20100002806 | APPARATUS FOR RECEIVING SIGNALS IN OFDM COMMUNICATION SYSTEM HAVING MULTIPLE ANTENNAS AND METHOD THEREOF - Provided are an apparatus for receiving signals in an OFDM communication system using multiple transmission/reception antennas and a method thereof. The method includes modulating a predetermined part of a data stream based on a multi-dimensional reception procedure to generate a first modulated data stream; regenerating a symbol corresponding to the modulated data stream; eliminating the regenerated symbol from a remained data stream; modulating the eliminated data stream to generate a second modulated data stream; and outputting an output signal obtained by serializing the first modulated data stream and the second modulated data stream. | 01-07-2010 |
| 20100031116 | METHOD FOR ENCODING LOW DENSITY PARITY CHECK CODES USING RESULT OF CHECKING PREVIOUSLY SPECIFIED PARITY BITS - There is provided to a method for encoding an LDPC (Low Density Parity Check) code using the result of checking a previously specified parity, including the steps of: forming a parity bit check matrix having a dual diagonal structure consisting of (N-K) rows for check nodes and (N-K) columns on the basis of the H matrix; calculating the values of all the parity bits by inserting a given binary value in sub-blocks, with the parity bit check matrix formed on the H matrix; if the values of the parity bits are incorrect, checking the parity bit corresponding to the sub-block located in the last part of the H matrix; searching the parity bit parts where the parity bit check result is represented as “1”; performing an XOR operation in sub-blocks on the parity bit part obtained through a simultaneous equation between the parity bits of the searched parity bit parts and the parity bit parts; and determining the value of the parity bit satisfying the condition that the value obtained by multiplying the H matrix by a code word vector. | 02-04-2010 |
| 20100260246 | TRANSMITTER AND RECEIVER FOR GIGA-BPS HIGH-THROUGHPUT WIRELESS COMMUNICATION SYSTEM WITH MULTIPLE ANTENNAS AND MULTIPLE BANDS - Provided is a transmitter and a receiver for a high-throughput wireless communication system. The transmitter includes a baseband transmitter, a DIF transmitter, and a RF transmitter. The baseband transmitter performs a MAC protocol process on transmission signals and reception signals and processes the transmission signals by dividing an entire transmission band into n bands in a physical layer process of the transmission data, where n is a natural number. The DIF transmitter combines transmission signals of each band from the baseband transmitter and outputs m channel signals corresponding to a number of transmission antennas, where m is a natural number. The RF transmitter modulates each of the channel signals transferred from the DIF transmitter and transmits the modulated signals through m antennas. | 10-14-2010 |
