| Patent application number | Description | Published |
|---|
| 20110103167 | SENSE AMPLIFIER AND SEMICONDUCTOR MEMORY APPARATUS INCLUDING THE SAME - A local sense amplifier of a semiconductor memory apparatus includes a read amplification unit configured to amplify data of first data lines and transfer the amplified data to second data lines during a read operation; and a write amplification unit configured to amplify data of the second data lines and transfer the amplified data to the first data lines during a write operation. | 05-05-2011 |
| 20110128039 | SEMICONDUCTOR CIRCUIT - A semiconductor circuit includes a pad, a pad driver connected to the pad at an output terminal thereof and configured to calibrate a voltage of the pad in response to code signals, a comparison section configured to compare a reference voltage and the voltage of the pad and generate a comparison signal, and a code generation section configured to calibrate code values of the code signals in response to the comparison signal. | 06-02-2011 |
| 20110156736 | SEMICONDUCTOR APPARATUS AND PROBE TEST METHOD THEREOF - Various embodiments of a semiconductor apparatus and related methods are disclosed. In one exemplary embodiment, a semiconductor apparatus may include a chip, scribe lanes disposed around the chip, and a probe test logic circuit for conducting a probe test on the chip. The probe test logic circuit is disposed on a portion of the scribe lanes. | 06-30-2011 |
| 20110169542 | DELAY CIRCUIT OF SEMICONDUCTOR MEMORY APPARATUS AND METHOD FOR DELAYING - A delay circuit of a semiconductor memory apparatus includes a decoding unit configured to decode a plurality of test signals and enable one of a plurality of control signals; a bias voltage generation unit configured to generate a first bias voltage and a second bias voltage depending upon the control signal enabled among the plurality of control signals; and a delay unit configured to determine a delay time depending upon levels of the first and second bias voltages, delay an input signal by the determined delay time, and output a resultant signal as an output signal. | 07-14-2011 |
| 20110187444 | VOLTAGE TRIMMING CIRCUIT OF SEMICONDUCTOR MEMORY APPARATUS - A voltage trimming circuit of a semiconductor memory apparatus may include a first voltage generation block configured to select voltage levels of a first node and a second node and divide a voltage between the first node and the second node to generate a first division voltage group; a second voltage generation block configured to select voltage levels of a third node and a fourth node and divide a voltage between the third node and the fourth node to generate a second division voltage group; a first switch block configured to select one division voltage of the first division voltage group to output the selected division voltage as a first reference voltage; and a second switch block configured to select one division voltage of the second division voltage group to output the selected division voltage as a second reference voltage. | 08-04-2011 |
| 20110188331 | SEMICONDUCTOR APPARATUS - A semiconductor apparatus having a plurality of chips stacked therein is disclosed. At least two of the plurality of chips are configured to receive a column command and generate a column control signal based on the column command. Generation timing of the column control signal generated based on a column command in one of the at least two of the plurality of chips substantially coincide with the generation timing in the other of the at least two of the plurality of chips. | 08-04-2011 |
| 20110204950 | DELAY CIRCUIT AND METHOD FOR DELAYING SIGNAL - A delay circuit includes: a delay unit configured to receive a clock signal, delay an input signal sequentially by a predetermined time interval, and output a plurality of first delayed signals; and an option unit configured to select one of the plurality of first delayed signals based on one or more select signals, and output a second delayed signal. | 08-25-2011 |
| 20110211406 | ADDRESS DELAY CIRCUIT - An address delay circuit of a semiconductor memory apparatus includes a control clock delay block configured to receive a clock as a first control clock in response to a first input control signal, and output external address as the first delayed address; a control clock input selecting delay block configured to receive the clock as a second control clock in response to a second input control signal, select whether to receive the external address or the first delayed address in response to the first input control signal, and output the selected address as the second delayed address; and a control clock input/output selecting delay block configured to receive the clock, select whether to receive the external address or the second delayed address in response to the second input control signal, and output the selected address as an internal address. | 09-01-2011 |
