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Jong Chern Lee
Jong Chern Lee, Ichon-Si KR
| Patent application number | Description | Published |
|---|---|---|
| 20100283518 | DELAY APPARATUS OF SEMICONDUCTOR INTEGRATED CIRCUIT AND METHOD OF CONTROLLING THE SAME - A delay apparatus of a semiconductor integrated circuit includes a control signal generating unit configured to generate a block control signal and a unit control signal in response to a delay control signal; a plurality of delay blocks, connected in series to each other, and configured to generate a delay clock signal by delaying an input clock signal, wherein each of the delay blocks includes a predetermined number of unit delayers, and the plurality of the delay blocks are configured to be selectively activated in response to the block control signal; and a minute delay unit including a predetermined number of unit delayers and configured to generate an output clock signal by delaying the delay clock signal by adjusting an activation number of the provided unit delayers in response to the unit control signal. | 11-11-2010 |
| 20100290306 | CIRCUIT AND METHOD FOR SHIFTING ADDRESS - A circuit for shifting an address includes a shift cell block configured to sequentially shift address signals in response to shift control signals and a control cell block configured to generate the shift control signals for activating the shift cell block in a column unit using sequentially shifted read commands or write commands. | 11-18-2010 |
| 20110102006 | CIRCUIT AND METHOD FOR TESTING SEMICONDUCTOR APPARATUS - A circuit for testing a semiconductor apparatus includes a test voltage applying unit configured to apply a test voltage to a first end of a through-silicon via (TSV) in response to a test mode signal and a detecting unit configured to be connected to a second end of the TSV and detect a current outputted from the second end of the TSV. | 05-05-2011 |
| 20110102065 | SEMICONDUCTOR APPARATUS AND CHIP SELECTION METHOD THEREOF - A semiconductor apparatus having a plurality of stacked chips includes: a plurality of latch units, each of which is disposed in a corresponding one of the plurality of chips and is configured to latch a clock signal and a frequency-divided signal at mutually different points of time to generate an chip identification signal of the corresponding one of the plurality of chips; and a plurality of chip selection signal generating units, each of which is disposed in the corresponding one of the plurality of chips and is configured to compare the chip identification signal of the corresponding one of the plurality of chips with a chip selection identification signal to generate a chip selection signal of the corresponding one of the plurality of chips, wherein the chip selection signal is configured to enable the corresponding one of the plurality of chips when the chip identification signal matches the chip selection identification signal. | 05-05-2011 |
| 20110102066 | SEMICONDUCTOR APPARATUS AND CHIP SELECTION METHOD THEREOF - A semiconductor apparatus having a plurality of stacked chips includes: a through silicon via (TSV) configured to couple the plurality of chips together and configured to be coupled in series to a plurality of voltage drop units; a plurality of signal conversion units, each of which is configured to convert a voltage outputted from the voltage drop unit of the corresponding one of the plurality of chips to a digital code signal and provide the digital code signal as chip identification signal of the corresponding one of the plurality of chips; and a plurality of chip selection signal generating units, each of which is configured to compare the chip identification signal with a chip selection identification signal to generate a chip selection signal of the corresponding one of the plurality of chips. | 05-05-2011 |
| 20110103156 | DATA INPUT/OUTPUT CIRCUIT AND SEMICONDUCTOR MEMORY APPARATUS HAVING THE SAME - A data input/output circuit includes a rank selecting section and a data input/output section. The rank selecting section is selectively connected to one of the first and second ranks in response to a chip selection signal, and outputs data to a connected rank or receives data from the connected rank. The data input/output section outputs the data transmitted from the rank selecting section through a data pad to an external device during a read operation, and outputs the data inputted to the data pad to the rank selecting section during a write operation. | 05-05-2011 |
Jong Chern Lee, Ichon-Shi KR
| Patent application number | Description | Published |
|---|---|---|
| 20110103167 | SENSE AMPLIFIER AND SEMICONDUCTOR MEMORY APPARATUS INCLUDING THE SAME - A local sense amplifier of a semiconductor memory apparatus includes a read amplification unit configured to amplify data of first data lines and transfer the amplified data to second data lines during a read operation; and a write amplification unit configured to amplify data of the second data lines and transfer the amplified data to the first data lines during a write operation. | 05-05-2011 |
| 20110128039 | SEMICONDUCTOR CIRCUIT - A semiconductor circuit includes a pad, a pad driver connected to the pad at an output terminal thereof and configured to calibrate a voltage of the pad in response to code signals, a comparison section configured to compare a reference voltage and the voltage of the pad and generate a comparison signal, and a code generation section configured to calibrate code values of the code signals in response to the comparison signal. | 06-02-2011 |
| 20110156736 | SEMICONDUCTOR APPARATUS AND PROBE TEST METHOD THEREOF - Various embodiments of a semiconductor apparatus and related methods are disclosed. In one exemplary embodiment, a semiconductor apparatus may include a chip, scribe lanes disposed around the chip, and a probe test logic circuit for conducting a probe test on the chip. The probe test logic circuit is disposed on a portion of the scribe lanes. | 06-30-2011 |
Jong Chern Lee, Ichon KR
| Patent application number | Description | Published |
|---|---|---|
| 20090231022 | PUMPING VOLTAGE GENERATING CIRCUIT - A pumping voltage generating circuit of a semiconductor memory apparatus, the pumping voltage generating circuit includes a detecting unit configured to compare a level of a pumping voltage with a level of a reference voltage to generate a detection signal, an oscillating signal generator configured to sequentially generate a first oscillating signal and a second oscillating signal in response to the detection signal, and to elevate frequencies of the first and second oscillating signals when the second oscillating signal is generated, a first pump configured to perform a pumping operation in response to the first oscillating signal, and a second pump configured to perform a pumping operation in response to the second oscillating signal, wherein output terminals of the first pump and the second pump are commonly connected, and the pumping voltage is output at the output terminals of the first pump and the second pump. | 09-17-2009 |
Jong Chern Lee, Chungcheongbuk-Do KR
| Patent application number | Description | Published |
|---|---|---|
| 20090066371 | BUFFER CIRCUIT WHICH OCCUPIES LESS AREA IN A SEMICONDUCTOR DEVICE - The present invention relates to a buffer circuit of a semiconductor memory device, and includes a common bias supply unit and a plurality of interface units having a differential amplifying structure. Each interface unit receives an input signal and differentially amplifies the input signal and a common bias. The common bias supply unit is driven by a reference voltage to provide the common bias signal to each of the interface units. The buffer circuit makes it possible to reduce the area occupied by the buffer circuit in a semiconductor memory device. | 03-12-2009 |
| 20090146697 | CIRCUIT FOR BUFFERING HAVING A COUPLER - The buffer circuit includes a differential amplifier differentially amplifying a reference node corresponding to a reference voltage and an input node corresponding to the input signal by sensing a potential difference of the reference voltage and the input signal. A coupling unit couples the input signal to the reference node, making it possible to improve the operating speed of the buffer circuit and operate normally when a level of the input signal or the reference voltage becomes low. | 06-11-2009 |
| 20090167417 | CHARGE PUMPING CIRCUIT WITH DECREASED CURRENT CONSUMPTION - A charge pumping circuit consumes less current by reducing the number of charge pumps operating simultaneously. The charge pumping circuit includes a voltage sensor that detects a level of a high voltage and outputs a control signal based on the detection result. An oscillator provides an oscillating clock signal in response to the control signal of the voltage sensor, and the oscillator sequentially outputs the clock signal as a plurality of clock signals having shifted phases A plurality of high-voltage pumps are disposed in a plurality of regions to pump the high voltage in response to the clock signals and a different phase is designated for each region. | 07-02-2009 |