Patent application number | Description | Published |
20090109723 | Quad SRAM Based One Time Programmable Memory - A quad SRAM based one time programmable memory cell is provided. Prior to programming, the memory cell operates as an SRAM memory cell. After programming, the memory cell operates as a one-time programmable non-volatile memory cell. The memory cell includes a storage element coupled at a first side to a first upper fuse and a first lower fuse and coupled at a second side to a second upper fuse and a second lower fuse. When the first upper fuse and second lower fuse are programmed, the storage element outputs a first value. When the second upper fuse and first lower fuse are programmed, the storage element outputs a second value. After programming the upper fuse acts as a pull-up fuse and the lower fuse acts as a pull-down fuse hold the state of the cell. | 04-30-2009 |
20090109724 | Differential Latch-Based One Time Programmable Memory - A differential latch-based one time programmable memory cell is provided. The differential latch-based one time programmable memory cell includes a differential latching amplifier having a first set of fuse devices coupled to the first input and a second set of fuse devices coupled to the second input. Only one set of fuse devices can be programmed in a memory cell. If one or more fuse devices in a set of fuse devices are programmed, the side having the programmed fuse will present a lower voltage at its input to the differential latching amplifier. Differential latching amplifier outputs a “0” or a “1” depending on the side having the programmed fuse. | 04-30-2009 |
20090237974 | Programmable memory cell - A disclosed embodiment is a programmable memory cell comprising an elevated ground node having a voltage greater than a common ground node by an amount substantially equal to a voltage drop across a trigger point adjustment element. In one embodiment, the trigger point adjustment element can be a diode. The trigger voltage of the programmable memory cell is raised closer to a supply voltage when current passes through the trigger point adjustment element during a write operation. The programmable memory cell can comprise a pair of cross-coupled inverters, and first and second programmable antifuses that can be coupled to each inverter in the pair of cross-coupled inverters. Since the trigger voltage of the programmable memory cell is raised closer to the supply voltage, a programmed antifuse can easily reach below the trigger voltage and result in a successful write operation even when the supply voltage is a low voltage. | 09-24-2009 |
20090237975 | One-time programmable memory cell - A disclosed embodiment is a programmable memory cell having improved IV characteristics comprising a thick oxide spacer transistor interposed between a programmable thin oxide antifuse and a thick oxide access transistor. The spacer transistor separates a rupture site formed during programming the programmable antifuse from the access transistor, so as to result in the improved IV characteristics. The programmable antifuse is proximate to one side of the spacer transistor, while the access transistor is proximate to an opposite side of the spacer transistor. The source region of the access transistor is coupled to ground, and the drain region of the access transistor also serves as the source region of the spacer transistor. The access transistor is coupled to a row line, while the spacer transistor and the programmable antifuse are coupled to a column line. The rupture site is formed during programming by applying a programming voltage to the programmable antifuse. | 09-24-2009 |
20100014340 | Quad SRAM Based One Time Programmable Memory - A differential latch-based one time programmable memory cell is provided. The differential latch-based one time programmable memory cell includes a differential latching amplifier having a first set of fuse devices coupled to the first input and a second set of fuse devices coupled to the second input. Only one set of fuse devices can be programmed in a memory cell. If one or more fuse devices in a set of fuse devices are programmed, the side having the programmed fuse will present a lower voltage at its input to the differential latching amplifier. Differential latching amplifier outputs a “0” or a “1” depending on the side having the programmed fuse. | 01-21-2010 |
20110255327 | METHOD AND SYSTEM FOR SPLIT THRESHOLD VOLTAGE PROGRAMMABLE BITCELLS - Methods and systems for split threshold voltage programmable bitcells are disclosed and may include selectively programming bitcells in a memory device by applying a high voltage to a gate terminal of the bitcells, where the programming burns a conductive hole in an oxide layer above a higher threshold voltage layer in a memory device. The bitcells may comprise an oxide layer and a doped channel, which may comprise a plurality of different threshold voltage layers. The plurality of different threshold voltage layers may comprise at least one layer with a higher threshold voltage and at least one layer with a lower threshold voltage. The oxide may comprise a gate oxide. The bitcell may comprise an anti-fuse device. The layer with a higher threshold voltage may be separated from an output terminal of the bitcell by the at least one layer with a lower threshold voltage. | 10-20-2011 |
20120195091 | Method and System for Split Threshold Voltage Programmable Bitcells - A memory device includes an antifuse. The antifuse is configured to program a bit cell of the memory device. The antifuse is configured with a PMOS device | 08-02-2012 |
20130307116 | Method and System for Split Threshold Voltage Programmable Bitcells - A bitcell can include an insulating area, a first doping, a second doping, and a gate terminal for the insulating area. The second doping can be proximate to the first doping and proximate to the insulating area. The second doping can be characterized by a lower threshold voltage than the first doping. The bitcell can be configured for programming by a voltage on the gate terminal that results in a conductive hole selectively burned in the insulating area between the gate terminal and the first doping. | 11-21-2013 |
20140183656 | Method and System for Split Threshold Voltage Programmable Bitcells - A bitcell may include an insulating region, a first doping proximate to the insulating region, and a second doping surrounding the first doping. The second doping can be characterized by a higher gate voltage breakdown than the first doping. Also, the bitcell may include a gate terminal, and the bitcell may be configured for programming by a voltage on the gate terminal that results in a conductive hole selectively burned in the insulating region between the gate terminal and the first doping. | 07-03-2014 |
20140376300 | DIFFERENTIAL BIT CELL - A differential bit cell includes two memory elements that are configured to have different states. Each of the two memory elements is connected to a respective switching element. Each of these switching elements may have process variances, which may result in a degradation of read and/or write margins. To mitigate the effect of such variances, another switching element is coupled to the two memory elements and their respective switching elements in a manner that couples the aforementioned switching elements in a parallel fashion. In this way, the mismatch effects between the switching elements can be negated during read operations. During programming operations, such a configuration allows for the programming of both memory elements to different states with a single current pulse and also reduces the effective resistance of the programming path. | 12-25-2014 |