Patent application number | Description | Published |
20080263339 | Method and Apparatus for Context Switching and Synchronization - A method, computer-readable medium, and apparatus for context switching between a first thread and a second thread. The method includes detecting an exception, wherein the exception is generated in response to receiving a packet of information directed to one of the first thread and the second thread, and in response to detecting the exception, invoking an exception handler. The exception handler is configured to execute one or more instructions removing access to at least a portion of a processor cache. The portion of the processor cache contains cached information for the first thread using a first address translation. Removing access to the portion of the processor cache prevents the second thread using a second address translation from accessing the cached information in the processor cache. The exception handler is also configured to branch to at least one of the first thread and the second thread. | 10-23-2008 |
20090049272 | METHOD FOR IMPROVING THE PERFORMANCE OF SOFTWARE-MANAGED TLB - Exemplary embodiments of the present invention comprise a method for the utilization of entry-replacement index hint information within a software-managed TLB. The method comprises receiving an address translation request at a TLB and retrieving the address translation information from a page table in the event of a miss lookup event at the TLB. The method further comprises retrieving index replacement hint information from a hardware component, wherein the hardware component is configured to execute a predetermined replacement algorithm and writing the address translation information to a TLB index referenced within the index replacement hint information. | 02-19-2009 |
20090049452 | Spawned Message State Determination - According to embodiments of the invention, methods and apparatus are provided for tracking the status or state of a message spawned or sent from one processing element to another processing element in a multiple core processing element network. According to embodiments of the invention, a message status tracker may be incorporated within a multiple core processing element network. As a message is spawned or sent from an originating processing element to a receiving processing element, a counter within the message status tracker may be incremented. If the receiving processing element spawns further messages in response to the received message, the counter may be further incremented. When a receiving processing element finishes a process in response to a received message, the receiving processing element may decrement the counter. When the counter is decremented to an original value (e.g., zero) the original message may be considered complete. | 02-19-2009 |
20090125706 | Software Pipelining on a Network on Chip - A network on chip (‘NOC’) that includes integrated processor (‘IP’) blocks, routers, memory communications controllers, and network interface controllers, with each IP block adapted to a router through a memory communications controller and a network interface controller, where each memory communications controller controlling communications between an IP block and memory, and each network interface controller controlling inter-IP block communications through routers, the NOC also including a computer software application segmented into stages, each stage comprising a flexibly configurable module of computer program instructions identified by a stage ID with each stage executing on a thread of execution on an IP block. | 05-14-2009 |
20090210592 | Network On Chip With A Low Latency, High Bandwidth Application Messaging Interconnect - A network on chip (‘NOC’) and methods of data processing on the NOC, the NOC including integrated processor (‘IP’) blocks, a data communications bus ( | 08-20-2009 |
20090210883 | Network On Chip Low Latency, High Bandwidth Application Messaging Interconnect - Data processing on a network on chip (‘NOC’) that includes integrated processor (‘IP’) blocks, routers, memory communications controllers, and network interface controllers, with each IP block adapted to a router through a memory communications controller and a network interface controller, where each memory communications controller controlling communications between an IP block and memory, each network interface controller controlling inter-IP block communications through routers, with each IP block also adapted to the network by a low latency, high bandwidth application messaging interconnect comprising an inbox and an outbox. | 08-20-2009 |
20090287885 | Administering Non-Cacheable Memory Load Instructions - Administering non-cacheable memory load instructions in a computing environment where cacheable data is produced and consumed in a coherent manner without harming performance of a producer, the environment including a hierarchy of computer memory that includes one or more caches backed by main memory, the caches controlled by a cache controller, at least one of the caches configured as a write-back cache. Embodiments of the present invention include receiving, by the cache controller, a non-cacheable memory load instruction for data stored at a memory address, the data treated by the producer as cacheable; determining by the cache controller from a cache directory whether the data is cached; if the data is cached, returning the data in the memory address from the write-back cache without affecting the write-back cache's state; and if the data is not cached, returning the data from main memory without affecting the write-back cache's state. | 11-19-2009 |
20090307714 | NETWORK ON CHIP WITH AN I/O ACCELERATOR - Data processing on a network on chip (‘NOC’) that includes IP blocks, routers, memory communications controllers, and network interface controllers; each IP block adapted to a router through a memory communications controller and a network interface controller; each memory communications controller controlling communication between an IP block and memory; each network interface controller controlling inter-IP block communications through routers; each IP block adapted to the network by a low latency, high bandwidth application messaging interconnect comprising an inbox and an outbox; a computer software application segmented into stages, each stage comprising a flexibly configurable module of computer program instructions identified by a stage ID with each stage executing on a thread of execution on an IP block; and at least one of the IP blocks comprising an input/output (‘I/O’) accelerator that administers at least some data communications traffic to and from the at least one IP block. | 12-10-2009 |
20100058026 | LOADING ENTRIES INTO A TLB IN HARDWARE VIA INDIRECT TLB ENTRIES - An enhanced mechanism for loading entries into a translation lookaside buffer (TLB) in hardware via indirect TLB entries. In one embodiment, if no direct TLB entry associated with the given virtual address is found in the TLB, the TLB is checked for an indirect TLB entry associated with the given virtual address. Each indirect TLB entry provides the real address of a page table associated with a specified range of virtual addresses and comprises an array of page table entries. If an indirect TLB entry associated with the given virtual address is found in the TLB, a computed address is generated by combining a real address field from the indirect TLB entry and bits from the given virtual address, a page table entry (PTE) is obtained by reading a word from a memory at the computed address, and the PTE is loaded into the TLB as a direct TLB entry. | 03-04-2010 |
20100058358 | METHOD AND APPARATUS FOR MANAGING SOFTWARE CONTROLLED CACHE OF TRANSLATING THE PHYSICAL MEMORY ACCESS OF A VIRTUAL MACHINE BETWEEN DIFFERENT LEVELS OF TRANSLATION ENTITIES - A method and a system for allowing a guest operating system (guest OS) to modify an entry in a TLB directly without an involvement of a hypervisor are disclosed. Upon receiving a guest TLB miss exception, a guest OS issues a TLBWE (TLB Write Entry) instruction to logic. The logic executes the TLBWE instruction at a supervisor mode without invoking a hypervisor. The TLB may incorporate entries in a guest page table and entries in a host page table. | 03-04-2010 |
20100115250 | CONTEXT SWITCHING AND SYNCHRONIZATION - A method, computer-readable medium, and apparatus for context switching between a first thread and a second thread. The method includes detecting an exception, wherein the exception is generated in response to receiving a packet of information directed to one of the first thread and the second thread, and in response to detecting the exception, invoking an exception handler. The exception handler is configured to execute one or more instructions removing access to at least a portion of a processor cache. The portion of the processor cache contains cached information for the first thread using a first address translation. Removing access to the portion of the processor cache prevents the second thread using a second address translation from accessing the cached information in the processor cache. The exception handler is also configured to branch to at least one of the first thread and the second thread. | 05-06-2010 |
20110173411 | TLB EXCLUSION RANGE - A system and method for accessing memory are provided. The system comprises a lookup buffer for storing one or more page table entries, wherein each of the one or more page table entries comprises at least a virtual page number and a physical page number; a logic circuit for receiving a virtual address from said processor, said logic circuit for matching the virtual address to the virtual page number in one of the page table entries to select the physical page number in the same page table entry, said page table entry having one or more bits set to exclude a memory range from a page. | 07-14-2011 |
20120215988 | Administering Non-Cacheable Memory Load Instructions - Administering non-cacheable memory load instructions in a computing environment where cacheable data is produced and consumed in a coherent manner without harming performance of a producer, the environment including a hierarchy of computer memory that includes one or more caches backed by main memory, the caches controlled by a cache controller, at least one of the caches configured as a write-back cache. Embodiments of the present invention include receiving, by the cache controller, a non-cacheable memory load instruction for data stored at a memory address, the data treated by the producer as cacheable; determining by the cache controller from a cache directory whether the data is cached; if the data is cached, returning the data in the memory address from the write-back cache without affecting the write-back cache's state; and if the data is not cached, returning the data from main memory without affecting the write-back cache's state. | 08-23-2012 |
20130007408 | METHOD AND APPARATUS FOR MANAGING SOFTWARE CONTROLLED CACHE OF TRANSLATING THE PHYSICAL MEMORY ACCESS OF A VIRTUAL MACHINE BETWEEN DIFFERENT LEVELS OF TRANSLATION ENTITIES - A method and a system for allowing a guest operating system (guest OS) to modify an entry in a TLB directly without an involvement of a hypervisor are disclosed. Upon receiving a guest TLB miss exception, a guest OS issues a TLBWE (TLB Write Entry) instruction to logic. The logic runs the TLBWE instruction at a supervisor mode without invoking a hypervisor. The TLB may incorporate entries in a guest page table and entries in a host page table. | 01-03-2013 |
20130024648 | TLB EXCLUSION RANGE - A system and method for accessing memory are provided. The system comprises a lookup buffer for storing one or more page table entries, wherein each of the one or more page table entries comprises at least a virtual page number and a physical page number; a logic circuit for receiving a virtual address from said processor, said logic circuit for matching the virtual address to the virtual page number in one of the page table entries to select the physical page number in the same page table entry, said page table entry having one or more bits set to exclude a memory range from a page. | 01-24-2013 |
20130179902 | Network On Chip With An I/O Accelerator - Data processing on a network on chip (‘NOC’) that includes IP blocks, routers, memory communications controllers, and network interface controllers; each IP block adapted to a router through a memory communications controller and a network interface controller; each memory communications controller controlling communication between an IP block and memory; each network interface controller controlling inter-IP block communications through routers; each IP block adapted to the network by a low latency, high bandwidth application messaging interconnect comprising an inbox and an outbox; a computer software application segmented into stages, each stage comprising a flexibly configurable module of computer program instructions identified by a stage ID with each stage executing on a thread of execution on an IP block; and at least one of the IP blocks comprising an input/output (‘I/O’) accelerator that administers at least some data communications traffic to and from the at least one IP block. | 07-11-2013 |