Patent application number | Description | Published |
20090063939 | ACS (ADD COMPARE SELECT) IMPLEMENTATION FOR RADIX-4 SOVA (SOFT-OUTPUT VITERBI ALGORITHM) - ACS (Add Compare Select) implementation for radix-4 SOVA (Soft-Output Viterbi Algorithm). A means is presented by which two trellis stages can be processes simultaneously and in parallel with one another (e.g., during a single clock cycle) thereby significantly increasing data throughput. During each processing iteration, the ACS module generates a hard decision for each of two trellis stages, as well as a corresponding reliability for each of the two hard decisions. Also, the ACS module is operable to generate the updated state metric for the state at the current trellis stage as well. Multiple operations are performed simultaneously and in parallel, and control logic circuitry and/or operations employed to select which of the multiple simultaneously-generated resultants is to be employed for each of the hard decisions, reliabilities, and next state metric for the current trellis stage. | 03-05-2009 |
20090063940 | REGISTER EXCHANGE NETWORK FOR RADIX-4 SOVA (SOFT-OUTPUT VITERBI ALGORITHM) - A means is presented by which two trellis stages can be processes simultaneously and in parallel with one another (e.g., during a single clock cycle) thereby significantly increasing data throughput. Any one or more modules within a REX module can be implemented using a radix-4 architecture to increase data throughput. For example, any or more of a SMU (Survivor Memory Unit), a PED (Path Equivalency Detector), and a RMU (Reliability Measure Unit) can be implemented in accordance with the principles of radix-4 decoding processing. | 03-05-2009 |
20090216942 | EFFICIENT MEMORY MANAGEMENT FOR HARD DISK DRIVE (HDD) READ CHANNEL - Efficient memory management for hard disk drive (HDD) read channel. The memory management presented herein can be broadly applied to any interface in which data is provided from a first location to a second location. A number of buffer units are employed, arranged into a number of slices, in which data is selectively written so that the information can be provided to the memory management architecture at a first rate, stored in the memory management architecture, and then output from the memory management architecture at a second rate. This ensures appropriate interfacing of information while also performing appropriate rate adjustment. The data is partitioned into a number of portions, and each portion also includes multiple subsets. On a subset basis, information of a first portion is provided to a first slice's buffer units, and information of a second portion is provided to a second slice's buffer units. | 08-27-2009 |
20110090734 | METHODS AND APPARATUS FOR STORING DATA IN A MULTI-LEVEL CELL FLASH MEMORY DEVICE WITH CROSS-PAGE SECTORS, MULTI-PAGE CODING AND PER-PAGE CODING - Methods and apparatus are provided for storing data in a multi-level cell flash memory device with cross-page sectors, multi-page coding and per-page coding. A single sector can be stored across a plurality of pages in the flash memory device. Per-page control is provided of the number of sectors in each page, as well the code and/or code rate used for encoding and decoding a given page, and the decoder or decoding algorithm used for decoding a given page. Multi-page and wordline level access schemes are also provided. | 04-21-2011 |
20110138114 | Methods and Apparatus For Interfacing Between a Flash Memory Controller and a Flash Memory Array - Methods and apparatus are provided for interfacing between a flash memory controller and a flash memory array. The interface comprises a communication channel between the flash memory controller and the flash memory array, wherein the communication channel carries data for a target cell in the flash memory array on a first edge of a clock signal and wherein the communication channel carries additional information for the target cell on a second edge of the clock signal. For an exemplary write access, the additional information comprises, for example, information about one or more aggressor cells associated with the target cell. For an exemplary read access, the additional information comprises, for example, soft information for the data for the target cell transmitted on the first edge. | 06-09-2011 |
20110191652 | MEMORY READ-CHANNEL WITH SELECTIVE TRANSMISSION OF ERROR CORRECTION DATA - A memory read-channel is provided with selective transmission of error correction data. The disclosed read-channel improves throughput and reduces power consumption when error correction codes are unnecessary. The data read from a memory device comprises user data, error detection data and error correction data. In one embodiment, the error detection data is evaluated to determine if there is a data error; and the error correction data is transmitted only if a data error is detected. In another variation, the error detection data is evaluated during data transmission to determine if there is a data error and the transmission is suspended if a data error is detected. Typically, the error detection data comprises a cyclic redundancy check and the error correction data comprises parity check data. | 08-04-2011 |
20110216586 | Methods And Apparatus For Intercell Interference Mitigation Using Modulation Coding - Methods and apparatus are provided for intercell interference mitigation using modulation coding. During programming of a flash memory, a modulation encoding is performed that selects one or more levels for programming the flash memory such that a reduced number of cells in the flash memory are programmed with a value that violates one or more predefined criteria. During a reading of a flash memory, a modulation decoding is performed that assigns one or more levels to cells in the flash memory such that a reduced number of cells in the flash memory are read with a value that violates one or more predefined criteria. The predefined criteria can be based, for example, on one or more of an amount of disturbance caused by the programmed cell; a voltage shift of a programmed cell: a voltage stored by a programmed cell; an amount of change in current through a programmed cell; and an amount of current through a programmed cell. | 09-08-2011 |
20110225350 | Methods and Apparatus for Soft Data Generation for Memory Devices Based Using Reference Cells - Methods and apparatus are provided for soft data generation for memory devices using reference cells. At least one soft data value is generated in a memory device by writing a known data to one or more reference cells; reading one or more of the reference cells; obtaining a read statistic based on the read one or more reference cells; and obtaining the at least one soft data value based on the obtained read statistic. The read statistics can optionally be obtained for one or more desired locations of a memory array; or for a given pattern, PATT, in one or more aggressor cells. The read statistic can optionally comprise asymmetric statistics obtained for a plurality of possible values. | 09-15-2011 |
20110239089 | Methods and Apparatus for Soft Data Generation for Memory Devices Using Decoder Performance Feedback - Methods and apparatus for soft data generation for memory devices using decoder performance feedback. At least one soft data value is generated in a memory device, by obtaining performance feedback from a decoder; obtaining an error statistic based on the performance feedback; and generating the at least one soft data value based on the obtained error statistic. The performance feedback comprises one or more of decoded bits, a number of erroneous bits based on data decoded by the decoder and a number of unsatisfied parity checks. | 09-29-2011 |
20110264980 | Systems and Methods for Low Density Parity Check Data Decoding - Various embodiments of the present invention provide systems and methods for decoding data. As an example, a data processing circuit is disclosed that includes a multi-tier decoding circuit having a first tier decoding circuit operable to decode portions of an encoded data set exhibiting low row weight, and a second tier decoding circuit operable to decode portions of an encoded data set exhibiting high row weight. | 10-27-2011 |
20120170678 | METHODS AND APPARATUS FOR TRELLIS-BASED MODULATION ENCODING - Methods and apparatus are provided for trellis-based modulation encoding. A signal is modulation encoded by encoding one or more blocks of the signal using one or more corresponding edges in a trellis, wherein each edge in the trellis has a corresponding bit pattern; selecting a winning path through the trellis based on at least one transition-based run-length constraint; and generating an encoded sequence using edges associated with the winning path. Exemplary trellis pruning techniques are also provided. The winning path through the trellis is selected by minimizing one or more modulation metrics. | 07-05-2012 |
20130007557 | Systems and Methods for Evaluating and Debugging LDPC Iterative Decoders - Various embodiments of the present invention provide systems and methods for evaluating and debugging a data decoder. For example, a data decoder circuit is discussed that includes an input memory, a data decoder operable to decode data from the input memory in one or more iterations, an output memory operable to store decoded data from the data decoder, and a test port operable to provide access to the input memory, the data decoder and the output memory. | 01-03-2013 |
20130061107 | Multi-Level LDPC Layer Decoder - Various embodiments of the present invention are related to methods and apparatuses for decoding data, and more particularly to methods and apparatuses for multi-level layered LDPC decoding. For example, in one embodiment an apparatus includes a variable node processor and a check node processor. The variable node processor is operable to generate variable node to check node messages and to calculate perceived values based on check node to variable node messages. The check node processor is operable to generate the check node to variable node messages and to calculate checksums based on variable node to check node messages. The check node processor includes a min finder circuit operable to identify a minimum, a next minimum and an index of minimum value in the variable node to check node messages. The variable node processor and check node processor are operable to perform layered multi-level decoding. | 03-07-2013 |
20130061112 | Multi-Level LDPC Layer Decoder - Various embodiments of the present invention provide methods and apparatuses for multi-level layer decoding of non-binary LDPC codes. For example, an apparatus is disclosed for layer decoding of multi-level low density parity check encoded data. The apparatus includes a low density parity check decoder operable to perform layered decoding of a plurality of circulant submatrices from an H matrix. The apparatus also includes a parity check calculator connected to the low density parity check decoder, operable to detect whether a stopping criterion has been met in the low density parity check decoder. The low density parity check decoder is also operable to end a decoding operation at less than a maximum number of iterations when the stopping criterion is met. | 03-07-2013 |
20130091397 | Systems and Methods for Parity Sharing Data Processing - Various embodiments of the present invention provide systems and methods for data processing. For example, a data processing system is disclosed that includes: a data detector circuit, a low density parity check data decoder circuit, and a processing circuit. The processing circuit is operable to: reconstitute a second encoded sub-codeword from a combination of data including the first encoded sub-codeword and the composite sub-codeword; and correct an error in one of the first encoded sub-codeword and the second encoded sub-codeword based at least in part on a combination of the first encoded sub-codeword, the second encoded sub-codeword, and the composite sub-codeword. | 04-11-2013 |
20130091400 | Systems and Methods for Parity Shared Data Encoding - Various embodiments of the present invention provide systems and methods for data processing. For example, a low density parity check encoding system is described that includes: a low density parity check encoder circuit, and a combining circuit. The low density parity check encoder circuit is operable to encode a first data set to yield a first low density parity check encoded sub-codeword, and to encode a second data set to yield a second low density parity check encoded sub-codeword. The combining circuit is operable to: generate a composite low density parity check sub-codeword by mathematically combining at least the first low density parity check encoded sub-codeword and the second low density parity check encoded sub-codeword; and combine at least the first low density parity check encoded sub-codeword and the composite low density parity check sub-codeword into an overall codeword. | 04-11-2013 |
20130132790 | Probability-Based Multi-Level LDPC Decoder - Various embodiments of the present invention are related to methods and apparatuses for decoding data, and more particularly to methods and apparatuses for probability-based multi-level LDPC decoding. For example, in one embodiment an apparatus includes a horizontal updater in a low density parity check decoder operable to iteratively perform row processing to update probabilities of multi-level symbol values, a vertical updater in the low density parity check decoder operable to iteratively perform column processing to update the probabilities of the multi-level symbol values, and a check sum calculation circuit operable to calculate total soft values for the multi-level symbol values. | 05-23-2013 |
20130173988 | Mixed Domain FFT-Based Non-Binary LDPC Decoder - Various embodiments of the present invention are related to methods and apparatuses for decoding data, and more particularly to methods and apparatuses for decoding data in a mixed domain FFT-based non-binary LDPC decoder. For example, in one embodiment an apparatus includes a message processing circuit operable to process variable node messages and check node messages in a log domain, and a check node calculation circuit in the low density parity check decoder operable to perform a Fast Fourier Transform-based check node calculation in a real domain. The message processing circuit and the check node calculation circuit perform iterative layer decoding. | 07-04-2013 |
20130198580 | Symbol Flipping Data Processor - Various embodiments of the present invention provide systems and methods for a symbol flipping data processor. For example, a symbol flipping data processor is disclosed that includes a data decoder in the symbol flipping data processor operable to perform error checking calculations, and a data detector in the symbol flipping data processor operable to perform symbol flipping in the data detector based at least in part on the error checking calculations, wherein the output of the data processor is generated at least in part based on the symbol flipping in the data detector. | 08-01-2013 |
20130275827 | Multi-Section Non-Binary LDPC Decoder - Various embodiments of the present invention provide systems and methods for decoding codewords in a multi-section non-binary LDPC decoder. For example, an LDPC decoder is disclosed that includes a variable node processor operable to perform variable node updates based at least in part on check node to variable node messages and to generate variable node to check node messages, and a check node processor operable to process the variable node to check node messages in groups across each of a plurality of sections of an H matrix and to generate the check node to variable node messages. | 10-17-2013 |
20130275986 | Data Processing System with Out of Order Transfer - Various embodiments of the present inventions provide systems and methods for data processing with out of order transfer. For example, a data processing system is disclosed that includes a data processor operable to process input blocks of data and to yield corresponding processed output blocks of data, wherein the processed output blocks of data are output from the data processor in an order in which their processing is completed, and a scheduler operable to receive processing priority requests for the input blocks of data and to assign processing resources in the data processor according to the priority requests. | 10-17-2013 |
20130297983 | Data Processing System with Failure Recovery - Various embodiments of the present invention provide systems and methods for a data processing system with failure recovery. For example, a data processing system is disclosed that includes a data processing circuit operable to process a block of data from an input and to yield a plurality of possible results based on the block of data, and an error detection circuit operable to test the plurality of possible results for errors and to report to the data processing circuit whether the plurality of possible results contain errors. The data processing system is operable to output any of the possible results in which the error detection circuit found no errors. | 11-07-2013 |
20130305114 | Symbol Flipping LDPC Decoding System - Various embodiments of the present inventions provide a symbol flipping LDPC decoding system. For example, a symbol flipping data processing system is disclosed that includes a low density parity check decoder operable to decode codewords and to identify unsatisfied parity checks, a symbol flipping controller operable to change values of at least one symbol in the codewords based on the unsatisfied parity checks to assist the low density parity check decoder to decode the codewords, a scheduler operable to control a decoding and symbol flipping mode in the low density parity check decoder and the symbol flipping controller, and a hard decision queue operable to store hard decisions for converged codewords from the low density parity check decoder. | 11-14-2013 |
20130332794 | Data Processing System with Retained Sector Reprocessing - Various embodiments of the present inventions are related to apparatuses and methods for data processing systems with retained sector reprocessing. For example, a data processing system is disclosed that includes a data processor operable to process blocks of data and to yield corresponding processed output blocks of data, and to retain the blocks of data for reprocessing when requested, and a scheduler operable to receive reprocessing requests for the retained blocks of data and to initiate a reprocessing operation in the data processor for the retained blocks of data. | 12-12-2013 |
20140006878 | Systems and Methods for Enhanced Accuracy NPML Calibration | 01-02-2014 |
20140068164 | EFFICIENT MEMORY CONTENT ACCESS - A memory content access interface may include, but is not limited to: a read-path memory partition; a write-path memory partition; and a memory access controller configured to regulate access to at least one of the read-path memory partition and the write-path memory partition by an external controller. | 03-06-2014 |
20140068389 | OPTIMIZED SCHEME AND ARCHITECTURE OF HARD DRIVE QUEUE DESIGN - Computer-implemented methods and systems may perform one or more operations including, but not limited to: receiving input data from a source; applying an interleaving protocol to the input data to generate at least one component code word; decoding the at least one component codeword; determining a first convergence value of at least one decoded component codeword; computing extrinsic data associated with the at least one component codeword according to the first convergence of at least one component codeword; determining a second convergence value associated with the at least one component codeword according to the extrinsic data associated with the at least one component codeword. | 03-06-2014 |
20140071558 | POWER MANAGEMENT FOR STORAGE DEVICE READ CHANNEL - A hard disk drive or other storage device comprises a storage medium, a read head configured to read data from the storage medium, and control circuitry coupled to the read head and configured to process data received from the read head. The control circuitry comprises read channel circuitry that includes a low-density parity check decoder or other type of decoder. | 03-13-2014 |
20140122971 | LEH Memory Module Architecture Design in the Multi-Level LDPC Coded Iterative System - A memory in a LDPC decoding system includes data banks organized into a ping-pong memory. The ping-pong memory is connected to an interleaver and a de-interleaver. The interleaver interleaves L values; the interleaved L values are then stored in the ping-pong memory. A LDPC decoder retrieves L values from the ping-pong memory and returns E values to the ping-pong memory. The de-interleaver de-interleaves the E values and sends data to a LE queue and HD queue. | 05-01-2014 |
20140122979 | Hardware Architecture and Implementation of Low Power Layered Multi-Level LDPC Decoder - A layered LDPC decoder sorts and selects a subset of message entries for processing based on entry size. MIN1 and MIN2 values for each message entry in the subset are truncated, and either the truncated values or non-truncated values are combined with a symbol vector based on whether the subset of message entries includes a variable node associated with the layer being processed. | 05-01-2014 |
20140126287 | Methods And Apparatus For Storing Data In A Multi-Level Cell Flash Memory Device With Cross-Page Sectors, Multi-Page Coding And Per-Page Coding - Methods and apparatus are provided for storing data in a multi-level cell flash memory device with cross-page sectors, multi-page coding and per-page coding. A single sector can be stored across a plurality of pages in the flash memory device. Per-page control is provided of the number of sectors in each page, as well as the code and/or code rate used for encoding and decoding a given page, and the decoder or decoding algorithm used for decoding a given page. Multi-page and wordline level access schemes are also provided. | 05-08-2014 |
20140126288 | Methods And Apparatus For Storing Data In A Multi-Level Cell Flash Memory Device With Cross-Page Sectors, Multi-Page Coding And Per-Page Coding - Methods and apparatus are provided for storing data in a multi-level cell flash memory device with cross-page sectors, multi-page coding and per-page coding. A single sector can be stored across a plurality of pages in the flash memory device. Per-page control is provided of the number of sectors in each page, as well as the code and/or code rate used for encoding and decoding a given page, and the decoder or decoding algorithm used for decoding a given page. Multi-page and wordline level access schemes are also provided. | 05-08-2014 |
20140126289 | Methods And Apparatus For Storing Data In A Multi-Level Cell Flash Memory Device With Cross-Page Sectors, Multi-Page Coding And Per-Page Coding - Methods and apparatus are provided for storing data in a multi-level cell flash memory device with cross-page sectors, multi-page coding and per-page coding. A single sector can be stored across a plurality of pages in the flash memory device. Per-page control is provided of the number of sectors in each page, as well as the code and/or code rate used for encoding and decoding a given page, and the decoder or decoding algorithm used for decoding a given page. Multi-page and wordline level access schemes are also provided. | 05-08-2014 |
20140129905 | Flexible Low Density Parity Check Code Seed - Various embodiments of the present inventions provide systems and methods for data processing with a flexible LDPC seed. | 05-08-2014 |
20140223114 | Buffer for Managing Data Samples in a Read Channel - The disclosure is directed to a system for managing data samples utilizing a time division multiplexing controller to allocate time slots for accessing a sample memory according to one or more modes of operation. The time division multiplexing controller is configured to allocate slots for concurrent access by a sample controller, a plurality of detectors, and a noise predictive calibrator when a normal mode is enabled. The time division multiplexing controller is further configured to allocate slots excluding at least one of the sample controller, the plurality of detectors, and the noise predictive calibrator from accessing the sample memory when a retry mode is enabled. In some embodiments, the time division multiplexing controller is further configured to allocate time slots for one or more clients other than the sample controller, the plurality of detectors, and the noise predictive calibrator. | 08-07-2014 |
20140337676 | Systems and Methods for Processing Data With Microcontroller Based Retry Features - A data processing system is disclosed including a data detector, a data decoder and a microcontroller. The data detector is operable to apply a data detection algorithm to generate detected values for data sectors. The data decoder is operable to apply a data decode algorithm to a decoder input derived from the detected values to yield decoded values. The microcontroller is operable to configure the data detector and the data decoder to apply the data detection algorithm and the data decode algorithm. | 11-13-2014 |