| Patent application number | Description | Published |
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| 20090063939 | ACS (ADD COMPARE SELECT) IMPLEMENTATION FOR RADIX-4 SOVA (SOFT-OUTPUT VITERBI ALGORITHM) - ACS (Add Compare Select) implementation for radix-4 SOVA (Soft-Output Viterbi Algorithm). A means is presented by which two trellis stages can be processes simultaneously and in parallel with one another (e.g., during a single clock cycle) thereby significantly increasing data throughput. During each processing iteration, the ACS module generates a hard decision for each of two trellis stages, as well as a corresponding reliability for each of the two hard decisions. Also, the ACS module is operable to generate the updated state metric for the state at the current trellis stage as well. Multiple operations are performed simultaneously and in parallel, and control logic circuitry and/or operations employed to select which of the multiple simultaneously-generated resultants is to be employed for each of the hard decisions, reliabilities, and next state metric for the current trellis stage. | 03-05-2009 |
| 20090063940 | REGISTER EXCHANGE NETWORK FOR RADIX-4 SOVA (SOFT-OUTPUT VITERBI ALGORITHM) - A means is presented by which two trellis stages can be processes simultaneously and in parallel with one another (e.g., during a single clock cycle) thereby significantly increasing data throughput. Any one or more modules within a REX module can be implemented using a radix-4 architecture to increase data throughput. For example, any or more of a SMU (Survivor Memory Unit), a PED (Path Equivalency Detector), and a RMU (Reliability Measure Unit) can be implemented in accordance with the principles of radix-4 decoding processing. | 03-05-2009 |
| 20090216942 | EFFICIENT MEMORY MANAGEMENT FOR HARD DISK DRIVE (HDD) READ CHANNEL - Efficient memory management for hard disk drive (HDD) read channel. The memory management presented herein can be broadly applied to any interface in which data is provided from a first location to a second location. A number of buffer units are employed, arranged into a number of slices, in which data is selectively written so that the information can be provided to the memory management architecture at a first rate, stored in the memory management architecture, and then output from the memory management architecture at a second rate. This ensures appropriate interfacing of information while also performing appropriate rate adjustment. The data is partitioned into a number of portions, and each portion also includes multiple subsets. On a subset basis, information of a first portion is provided to a first slice's buffer units, and information of a second portion is provided to a second slice's buffer units. | 08-27-2009 |
| 20110090734 | METHODS AND APPARATUS FOR STORING DATA IN A MULTI-LEVEL CELL FLASH MEMORY DEVICE WITH CROSS-PAGE SECTORS, MULTI-PAGE CODING AND PER-PAGE CODING - Methods and apparatus are provided for storing data in a multi-level cell flash memory device with cross-page sectors, multi-page coding and per-page coding. A single sector can be stored across a plurality of pages in the flash memory device. Per-page control is provided of the number of sectors in each page, as well the code and/or code rate used for encoding and decoding a given page, and the decoder or decoding algorithm used for decoding a given page. Multi-page and wordline level access schemes are also provided. | 04-21-2011 |
| 20110138114 | Methods and Apparatus For Interfacing Between a Flash Memory Controller and a Flash Memory Array - Methods and apparatus are provided for interfacing between a flash memory controller and a flash memory array. The interface comprises a communication channel between the flash memory controller and the flash memory array, wherein the communication channel carries data for a target cell in the flash memory array on a first edge of a clock signal and wherein the communication channel carries additional information for the target cell on a second edge of the clock signal. For an exemplary write access, the additional information comprises, for example, information about one or more aggressor cells associated with the target cell. For an exemplary read access, the additional information comprises, for example, soft information for the data for the target cell transmitted on the first edge. | 06-09-2011 |
| 20110191652 | MEMORY READ-CHANNEL WITH SELECTIVE TRANSMISSION OF ERROR CORRECTION DATA - A memory read-channel is provided with selective transmission of error correction data. The disclosed read-channel improves throughput and reduces power consumption when error correction codes are unnecessary. The data read from a memory device comprises user data, error detection data and error correction data. In one embodiment, the error detection data is evaluated to determine if there is a data error; and the error correction data is transmitted only if a data error is detected. In another variation, the error detection data is evaluated during data transmission to determine if there is a data error and the transmission is suspended if a data error is detected. Typically, the error detection data comprises a cyclic redundancy check and the error correction data comprises parity check data. | 08-04-2011 |
| 20110216586 | Methods And Apparatus For Intercell Interference Mitigation Using Modulation Coding - Methods and apparatus are provided for intercell interference mitigation using modulation coding. During programming of a flash memory, a modulation encoding is performed that selects one or more levels for programming the flash memory such that a reduced number of cells in the flash memory are programmed with a value that violates one or more predefined criteria. During a reading of a flash memory, a modulation decoding is performed that assigns one or more levels to cells in the flash memory such that a reduced number of cells in the flash memory are read with a value that violates one or more predefined criteria. The predefined criteria can be based, for example, on one or more of an amount of disturbance caused by the programmed cell; a voltage shift of a programmed cell: a voltage stored by a programmed cell; an amount of change in current through a programmed cell; and an amount of current through a programmed cell. | 09-08-2011 |
| 20110225350 | Methods and Apparatus for Soft Data Generation for Memory Devices Based Using Reference Cells - Methods and apparatus are provided for soft data generation for memory devices using reference cells. At least one soft data value is generated in a memory device by writing a known data to one or more reference cells; reading one or more of the reference cells; obtaining a read statistic based on the read one or more reference cells; and obtaining the at least one soft data value based on the obtained read statistic. The read statistics can optionally be obtained for one or more desired locations of a memory array; or for a given pattern, PATT, in one or more aggressor cells. The read statistic can optionally comprise asymmetric statistics obtained for a plurality of possible values. | 09-15-2011 |
