| Patent application number | Description | Published |
|---|
| 20090079747 | Distributed Antialiasing In A Multiprocessor Graphics System - Multiprocessor graphics systems support distributed antialiasing. In one embodiment, two (or more) graphics processors each render a version of the same image, with a difference in the sampling location (or locations) used for each pixel. A display head combines corresponding pixels generated by different graphics processors to produce an antialiased image. This distributed antialiasing technique can be scaled to any number of graphics processors. | 03-26-2009 |
| 20090085928 | ANTIALIASING USING MULTIPLE DISPLAY HEADS OF A GRAPHICS PROCESSOR - Multiple display heads of a single graphics processor are exploited to perform antialiasing and other processing tasks. In one embodiment, two display heads of the same graphics processor are coupled to each other in a master/slave configuration via a pixel transfer path. The “master” display head receives pixels from the “slave” display head in addition to its own pixels, and pixel selection logic in the master display head can blend the two pixels or select either one to the exclusion of the other. If the two pixels correspond to different sampling locations in the same display pixel, the blended pixel is an antialiased pixel. | 04-02-2009 |
| 20090189908 | Display Balance / Metering - Method, apparatuses, and systems are presented for processing a sequence of images for display using a display device involving operating a plurality of graphics devices, including at least one first graphics device that processes certain ones of the sequence of images, including a first image, and at least one second graphics device that processes certain other ones of the sequence of images, including a second image, delaying processing of the second image by the at least one second graphics device, by a specified duration, relative to processing of the first image by the at least one first graphics device, to stagger pixel data output for the first image and pixel data output for the second image, and selectively providing output from the at least one first graphics device and the at least one second graphics device to the display device. | 07-30-2009 |
| 20090273603 | DETECTING CONNECTION TOPOLOGY IN A MULTI PROCESSOR GRAPHICS SYSTEM - Multiple graphics processors in a graphics processing system are interconnected in a unidirectional or bidirectional ring topology, allowing pixels to transferred from any one graphics processor to any other graphics processor. The system can automatically identify one or more “master” graphics processors to which one or more monitors are connected and configures the links of the ring such that one or more other graphics processors can deliver pixels to the master graphics processor, facilitating distributed rendering operations. The system can also automatically detect the connections or lack thereof between the graphics processors. | 11-05-2009 |
| 20110090232 | GRAPHICS PROCESSING SYSTEMS WITH MULTIPLE PROCESSORS CONNECTED IN A RING TOPOLOGY - Multiple graphics processors in a graphics processing system are interconnected in a unidirectional or bidirectional ring topology, allowing pixels to transferred from any one graphics processor to any other graphics processor. The system can automatically identify one or more “master” graphics processors to which one or more monitors are connected and configures the links of the ring such that one or more other graphics processors can deliver pixels to the master graphics processor, facilitating distributed rendering operations. The system can also automatically detect the connections or lack thereof between the graphics processors. | 04-21-2011 |
| 20110102448 | VERTEX ATTRIBUTE BUFFER FOR INLINE IMMEDIATE ATTRIBUTES AND CONSTANTS - One embodiment of the present invention sets forth a technique for providing primitives and vertex attributes to the graphics pipeline. A primitive distribution unit constructs the batches of primitives and writes inline attributes and constants to a vertex attribute buffer (VAB) rather than passing the inline attributes directly to the graphics pipeline. A batch includes indices to attributes, where the attributes for each vertex are stored in a different VAB. The same VAB may be referenced by all of the vertices in a batch or different VABs may be referenced by different vertices in one or more batches. The batches are routed to the different processing engines in the graphics pipeline and each of the processing engines reads the VABs as needed to process the primitives. The number of parallel processing engines may be changed without changing the width or speed of the interconnect used to write the VABs. | 05-05-2011 |
