| Patent application number | Description | Published |
|---|
| 20080272847 | SIGNALING SYSTEM WITH LOW-POWER AUTOMATIC GAIN CONTROL - An integrated circuit device includes a variable-gain amplifier, memory circuit and gain control update circuit. The variable-gain amplifier generates an amplified signal having an amplitude according to a gain control value that is stored, at least during a first interval, within the memory circuit. The update circuit generates an updated gain control value based on the amplified signal during the first interval, and outputs the updated gain control value to the memory circuit to be stored therein at a conclusion of the first interval. | 11-06-2008 |
| 20090015340 | Phase Controlled Oscillator Circuit with Input Signal Coupler - An oscillating signal in an oscillator is caused to phase shift toward the phase of an input signal coupled to the oscillating signal. The resonant frequency of the oscillator is about equal to an integer multiple of the frequency of the input signal. The input signal may be generated in a pulse generator to have an input pulse duration less than or equal to that of the oscillating signal. The oscillator circuit may be used as a filter to filter pulse width variations or to filter jitter from a reference clock. The oscillator circuit may also serve as a buffer by amplifying the input signal. Phase interpolation can be obtained by coupling at least one input signal with at least one oscillating signal. | 01-15-2009 |
| 20090059642 | Memory Controller With Multi-Modal Reference Pad - A memory controller operates in two modes to support different types of memory devices. In a first mode, the memory controller distributes a dedicated reference voltage with each of a plurality of signal bundles to a corresponding plurality of memory devices. The reference voltages are conveyed using pads that are alternatively used for e.g. timing-reference signals in a second mode, so the provision for bundle-specific reference voltages need not increase the number of pads on the memory controller. | 03-05-2009 |
| 20090201090 | SIGNALING SYSTEM WITH LOW-POWER AUT0MATIC GAIN CONTROL - An integrated circuit device includes a variable-gain amplifier, memory circuit and gain control update circuit. The variable-gain amplifier generates an amplified signal having an amplitude according to a gain control value that is stored, at least during a first interval, within the memory circuit. The update circuit generates an updated gain control value based on the amplified signal during the first interval, and outputs the updated gain control value to the memory circuit to be stored therein at a conclusion of the first interval. | 08-13-2009 |
| 20100066450 | High-Speed Low-Power Differential Receiver - A low-voltage differential communication system includes a low- and programmable-swing voltage-mode transmitter that delivers a low-voltage differential signal to a receiver via differential channel. The receiver employs two input transistors, each in a common-gate configuration, to recover the low-voltage differential signal. A current source in the receiver biases the input transistors such that their source voltages are nominally biased at the common-mode voltage of the differential signal, and their gate-source voltages remain essentially constant with common-mode-voltage fluctuations. | 03-18-2010 |
| 20100085100 | Low-Power Clock Generation and Distribution Circuitry - A communication IC includes a power-efficient clock-distribution system. A control loop monitors and adjusts the peak and trough voltages of a clock signal. The clock signal can be adaptively adjusted to center the peak and trough voltages about the switching threshold voltage of a clock buffer. The voltage swing of the clock signal can thus be made small and, as a consequence, power efficient. The control loop can monitor and control more than one clock signal. | 04-08-2010 |
| 20100283547 | SIGNALING SYSTEM WITH LOW-POWER AUTOMATIC GAIN CONTROL - An integrated circuit receiver includes a first channel comprising an amplifier responsive to a first gain control value in a first mode to receive an input signal and generate a first amplified signal having a transition rate. Detection circuitry in the first channel detects transitions in the first amplified signal in accordance with a detected transition rate. The detected transition rate is based on the first gain control value. Gain control logic adjusts the first gain control value based on a desired detected transition rate. The gain control logic generates a second gain control value for use during a second mode. The second gain control value being based on the first gain control value. | 11-11-2010 |
| 20100309791 | EDGE-BASED LOSS-OF-SIGNAL DETECTION - Systems and methods are provided for edge-based loss-of-signal (LOS) detection. In a receiver, a receiver port receives a data signal. A clock and data recovery (CDR) mechanism coupled to the receive port derives one or more clock signals. An LOS signal generation mechanism generates an LOS signal based on edge glitches which occur when the receive port does not receive usable data. | 12-09-2010 |
| 20110158031 | SIGNAL CALIBRATION METHODS AND APPARATUSES - In a signal calibration scheme, a desired phase relationship is maintained between a set of signals. For example, in some aspects the desired phase of a clock tree generated from a high speed reference clock signal may be maintained by detecting phase differences between a low speed reference clock signal and low speed clock signals associated with different phases of the clock tree. In some aspects, the desired phase of a clock tree may be maintained by detecting framing offsets that occur through the use of the clock tree. | 06-30-2011 |
