| Patent application number | Description | Published |
|---|
| 20080217748 | LOW COST AND LOW COEFFICIENT OF THERMAL EXPANSION PACKAGING STRUCTURES AND PROCESSES - A method for producing a chip carrier, the method includes selecting at least one core with a low coefficient of thermal expansion; selecting at least one build-up layer wherein each build-up layer includes a dielectric material and circuitry; and connecting selected cores and selected build-up layers together in a pre-determined order. | 09-11-2008 |
| 20080272177 | CONDUCTIVE BONDING MATERIAL FILL TECHNIQUES - A system provides solder into cavities in a circuit supporting substrate. The system places a fill head in substantial contact with a circuit supporting substrate. The circuit supporting substrate includes at least one cavity. A linear motion or a rotational motion is provided to at least one of the circuit supporting substrate and the fill head while the fill head is in substantial contact with the circuit supporting substrate. Solder is forced out of the fill head toward the circuit supporting substrate. The solder is provided into the at least one cavity contemporaneous with the at least one cavity being in proximity to the fill head. The system brings a second circuit supporting substrate in close proximity to the circuit supporting substrate, at least one receiving pad on the second circuit supporting substrate substantially contacts the conductive bonding material of the at least one cavity. | 11-06-2008 |
| 20080282114 | METHOD TO ENHANCE MICRO-C4 RELIABILITY BY REDUCING THE IMPACT OF HOT SPOT PULSING - A system for reducing an impact of hot spot, pulsing of a semiconductor device including: first generating means for generating a plurality of local op-codes; a sequencer for augmenting customer op-codes with the plurality of local op-codes; selecting means for selecting one or more of the randomly arriving customer op-codes awaiting execution; monitoring means for tracking which of the one or more randomly arriving customer op-codes have been selected; separating means for separating the plurality of local op-codes from the one or more customer op-codes; storing means for storing one or more data related to the processing of the plurality of local op-codes and the customer op-codes; and second generating means for generating an output for a customer corresponding to that customer op-code while gainfully employing an output generated by local op-codes for system health monitoring purpose. | 11-13-2008 |
| 20080284037 | Apparatus and Methods for Constructing Semiconductor Chip Packages with Silicon Space Transformer Carriers - Apparatus and methods are provided for high density packaging of semiconductor chips using silicon space transformer chip level package structures, which allow high density chip interconnection and/or integration of multiple chips or chip stacks high I/O interconnection and heterogeneous chip or function integration. | 11-20-2008 |
| 20080315409 | DIRECT EDGE CONNECTION FOR MULTI-CHIP INTEGRATED CIRCUITS - The present invention allows for direct chip-to-chip connections using the shortest possible signal path. | 12-25-2008 |
| 20090008057 | ROTATIONAL FILL TECHNIQUES FOR INJECTION MOLDING OF SOLDER - A system and method for injection molding conductive bonding material into a plurality of cavities in a non-rectangular mold is disclosed. The method comprises aligning a fill head with a non-rectangular mold. The non-rectangular mold includes a plurality of cavities. The fill head is placed in substantial contact with the non-rectangular mold. Rotational motion is provided to at least one of the non-rectangular mold and the fill head while the fill head is in substantial contact with the non-rectangular mold. Conductive bonding material is forced out of the fill head toward the non-rectangular mold. The conductive bonding material is provided into at least one cavity of the plurality of cavities contemporaneous with the at least one cavity being in proximity to the fill head. | 01-08-2009 |
| 20090014856 | MICROBUMP SEAL - A sealable microelectronic device providing mechanical stress endurance which includes a semiconductor substrate. A substantially continuous sealing element is positioned adjacent an outer periphery and between a microelectronic component and the semiconductor substrate, or another microelectronic component. The sealing element seals the microelectronic component to the substrate or another microelectronic component, and provides structural support to the microelectronic device. | 01-15-2009 |
| 20090039472 | STRUCTURE AND METHOD FOR CREATING RELIABLE DEEP VIA CONNECTIONS IN A SILICON CARRIER - A process and structure for enabling the creation of reliable electrical through-via connections in a semiconductor substrate and a process for filling vias. Problems associated with under etch, over etch and flaring of deep Si RIE etched through-vias are mitigated, thereby vastly improving the integrity of the insulation and metallization layers used to convert the through-vias into highly conductive pathways across the Si wafer thickness. By using an insulating collar structure in the substrate in one case and by filling the via in accordance with the invention in another case, whole wafer yield of electrically conductive through vias is greatly enhanced. | 02-12-2009 |
| 20090085217 | SEMICONDUCTOR DEVICE AND METHOD OF MAKING SEMICONDUCTOR DEVICE - A semiconductor device includes a carrier, a semiconductor chip formed on the carrier, and a micro-chip which is electrically connected to the chip, and includes a thickness which is less than a thickness of the chip. | 04-02-2009 |
| 20090201038 | TEST HEAD FOR FUNCTIONAL WAFER LEVEL TESTING, SYSTEM AND METHOD THEREFOR - A test head, system and method allowing functional wafer level testing of a test wafer, a die under test or a wafer under test, including at least one chip. The test head includes a semiconductor wafer and a series of protrusions in the semiconductor wafer. Each protrusion of the series of protrusions includes an electrical interconnection on a bottom surface of the semiconductor wafer, and a corresponding probe tip protruding from a top surface of the semiconductor wafer for establishing an electrical connection with a solder bump of the test wafer. The series of protrusion probe tips includes a pitch range of about 1 μm to about 100 μm. | 08-13-2009 |
| 20090290282 | MODULAR CHIP STACK AND PACKAGING TECHNOLOGY WITH VOLTAGE SEGMENTATION, REGULATION, INTEGRATED DECOUPLING CAPACITANCE AND COOLING STRUCTURE AND PROCESS - An electronic apparatus includes an electronic component electrically connected to a substrate positioned beneath the electronic component. A member includes a plurality of decoupling capacitors having different voltages, and the decoupling capacitors are electrically connected to the electronic component. A plurality of voltage planes in the member are electrically connected to the decoupling capacitors. The decoupling capacitors, via the voltage planes in the member, provide different voltages to the voltage planes and thus the electronic component. | 11-26-2009 |
| 20090298236 | Integrated Module for Data Processing System - An apparatus for an integrated module. A silicon carrier with through-silicon vias has a plurality of die connected to a top side of the silicon carrier. In addition, a substrate is connected to a bottom side of the silicon carrier. The substrate is coupled to the plurality of die via the through-silicon vias. | 12-03-2009 |
| 20090301685 | FLEXIBLE NOZZLE FOR INJECTION MOLDED SOLDER - A flexible nozzle for injection molded solder of utilizing a flexible nozzle for injection molded solder applications. In order to be able to efficiently carry out the injection molded soldering process, there is utilized a compliant or flexible solder-dispensing nozzle structure, which is particularly advantageously adapted to be utilized with circular or round molds. In this connection, the tip of the nozzle, which provides for the discharge of the solder, provides a series of small holes or apertures for extruding the solder under pressure from at least one solder reservoir. In one embodiment, there may be employed a single solder reservoir with which there communicates a plurality of discharge apertures or holes for extruding the solder so as to fill suitable cavities or recesses formed in a facing surface of a mold for injection molded solder. Alternatively, rather than dispensing or extruding the solder from a single reservoir through a plurality of holes or discharge apertures, each respective aperture or a group of apertures may be connected to, respectively, a separate solder reservoir of a plurality of reservoirs subjected to pressure to facilitate the solder extrusion onto the mold surface. | 12-10-2009 |
| 20090305465 | MICROBUMP SEAL - A sealable microelectronic device providing mechanical stress endurance which includes a semiconductor substrate. A substantially continuous sealing element is positioned adjacent an outer periphery and between a microelectronic component and the semiconductor substrate, or another microelectronic component. The sealing element seals the microelectronic component to the substrate or another microelectronic component, and provides structural support to the microelectronic device. | 12-10-2009 |
| 20090309234 | SEMICONDUCTOR DEVICE AND METHOD OF MAKING SEMICONDUCTOR DEVICE - A semiconductor device includes a semiconductor chip, and a micro-chip which is electrically connected to the chip, and includes a thickness which is less than a thickness of the chip. | 12-17-2009 |
| 20090311828 | APPARATUS AND METHODS FOR CONSTRUCTING SEMICONDUCTOR CHIP PACKAGES WITH SILICON SPACE TRANSFORMER CARRIERS - Apparatus and methods are provided for high density packaging of semiconductor chips using silicon space transformer chip level package structures, which allow high density chip interconnection and/or integration of multiple chips or chip stacks high I/O interconnection and heterogeneous chip or function integration. | 12-17-2009 |
| 20100013073 | APPARATUS AND METHODS FOR CONSTRUCTING SEMICONDUCTOR CHIP PACKAGES WITH SILICON SPACE TRANSFORMER CARRIERS - Apparatus and methods are provided for high density packaging of semiconductor chips using silicon space transformer chip level package structures, which allow high density chip interconnection and/or integration of multiple chips or chip stacks high I/O interconnection and heterogeneous chip or function integration. | 01-21-2010 |
| 20100044856 | ELECTRONIC PACKAGE WITH A THERMAL INTERPOSER AND METHOD OF MANUFACTURING THE SAME - An electronic package includes a die including a thermal interface material through which a primary heat flux path is enabled for conducting heat from the die, an organic substrate, and a thermal interposer provided between the organic substrate and the die, the thermal interposer having an area extending beyond a footprint of the die, the area including the thermal interface material, the thermal interposer conducting heat generated by the die through the thermal interface material such that an auxiliary heat flux path for conducting heat generated in the die is enabled. | 02-25-2010 |
| 20100276813 | INJECTION MOLDED SOLDERING PROCESS AND ARRANGEMENT FOR THREE-DIMENSIONAL STRUCTURES - A method of implementing an injection molded soldering process for three-dimensional structures, particularly, such as directed to three-dimensional semiconductor chip stacking. Also provide is an arrangement for implementing the injection molded soldering (IMS) process. Pursuant to an embodiment of the invention, the joining of the semiconductor chip layers with a substrate is implemented, rather than by means of currently known wire bond stacking, through the intermediary of columns of solder material formed by the IMS process, thereby providing electrical advantages imparted by the flip chip interconnect structures. In this connection, various diversely dimensioned solder column interconnects allow for simple and dependable connections to a substrate by a plurality of superimposed layers or stacked arrays of semiconductor components, such as semiconductor chips. In accordance with a further aspect, it is possible to derive a unique design for an IMS mold structure, which contains cavities for forming the columnar fill of solder, and which also incorporates further cavities acting as cutouts for dies or the positioning of other electronic packages or modules. | 11-04-2010 |
