| Patent application number | Description | Published |
|---|
| 20080197488 | BOWED WAFER HYBRIDIZATION COMPENSATION - A planarizing method performed on a non-planar wafer involves forming electrically conductive posts extending through a removable material, each of the posts having a length such that a top of each post is located above a plane defining a point of maximum deviation for the wafer, concurrently smoothing the material and posts so as to form a substantially planar surface, and removing the material. An apparatus includes a non planar wafer having contacts thereon, the wafer having a deviation from planar by an amount that is greater than a height of at least one contact on the wafer, and a set of electrically conductive posts extending away from a surface of the wafer, the posts each having a distal end, the distal ends of the posts collectively defining a substantially flat plane. | 08-21-2008 |
| 20080197508 | PLATED PILLAR PACKAGE FORMATION - A method involves plating pillars of electrically conductive material up from a seed layer located on a substrate, surrounding the pillars with a fill material so that the pillars and fill material collectively define a first package, and removing the substrate from the first package. | 08-21-2008 |
| 20080197893 | VARIABLE OFF-CHIP DRIVE - A driver circuit includes a set of selectable drivers each having an individual drive capability, the drivers being selectable such that i) when a subset of the drivers is selected, a signal will be driven by the drivers at a first drive level, and ii) when the subset of the drivers and at least one additional driver is selected, signal will be driven by the drivers at a level that is greater than the first level by a level of drive provided by the least one additional driver. | 08-21-2008 |
| 20080200022 | POST-SEED DEPOSITION PROCESS - A method involves pattern etching a photoresist that is located on a wafer that contains a deposited seed layer to expose portions of the seed layer, plating the wafer so that plating metal builds up on only the exposed seed layer until the plating metal has reached an elevation above the seed layer that is at least equal to a thickness of the seed layer, removing the solid photoresist, and removing seed layer exposed by removal of the photoresist and plated metal until all of the exposed seed layer has been removed. | 08-21-2008 |
| 20080245846 | HEAT CYCLE-ABLE CONNECTION - A method of creating an electrical connection involves providing a pair of contacts each on one of two different chips, the pair of contacts defining a volume therebetween, the volume containing at least two compositions each having melting points, the compositions having been selected such that heating to a first temperature will cause a change in at least one of the at least two compositions such that the change will result in a new composition having a new composition melting point of a second temperature, greater than the first temperature and the melting point of at least a first of the at least two compositions, and heating the pair of contacts and the at least two compositions to the first temperature. | 10-09-2008 |
| 20080246145 | MOBILE BINDING IN AN ELECTRONIC CONNECTION - A method of creating an electrical contact involves locating a barrier material at a location for an electrical connection, providing an electrically conductive bonding metal on the barrier material, the electrically conductive bonding metal having a diffusive mobile component, the volume of barrier material and volume of diffusive mobile component being selected such that the barrier material volume is at least 20% of the volume of the combination of the barrier material volume and diffusive mobile component volume. An electrical connection has an electrically conductive bonding metal between two contacts, a barrier material to at least one side of the electrically conductive bonding metal, and an alloy, located at an interface between the barrier material and the electrically conductive bonding metal. The alloy includes at least some of the barrier material, at least some of the bonding metal, and a mobile material. | 10-09-2008 |
| 20080258284 | ULTRA-THIN CHIP PACKAGING - A packaging method involves attaching a first chip to a stable base, forming contact pads at locations on the stable base, applying a medium onto the stable base such that it electrically insulates sides of the first chip, forming electrical paths on the medium, attaching a second chip to the first chip to form an assembly, and removing the stable base. A package has at least two chips electrically connected to each other, at least one contact pad, an electrically conductive path extending from the contact pad to a contact point on at least one of the chips, a planarizing medium, and a coating material on top of the planarizing medium. | 10-23-2008 |
| 20080261392 | CONDUCTIVE VIA FORMATION - A method involves depositing a first electrically conductive material, using a deposition technique, into a via formed in a material, the via having a diameter at a surface of the material of less than about 10 μm and a depth of greater than about 50 μm, so as to form a seed layer within the via, then creating a thickening layer on top of the seed layer by electrolessly plating the seed layer with a second electrically conductive material without performing any activation process within the via between via formation and the creating the thickening layer, and then electroplating a conductor metal onto the thickening layer until a volume bounded by the thickening layer within the via is filled with the conductor metal. | 10-23-2008 |
| 20090267219 | ULTRA-THIN CHIP PACKAGING - A packaging method involves attaching a first chip to a stable base, forming contact pads at locations on the stable base, applying a medium onto the stable base such that it electrically insulates sides of the first chip, forming electrical paths on the medium, attaching a second chip to the first chip to form an assembly, and removing the stable base. A package has at least two chips electrically connected to each other, at least one contact pad, an electrically conductive path extending from the contact pad to a contact point on at least one of the chips, a planarizing medium, and a coating material on top of the planarizing medium. | 10-29-2009 |
| 20090269888 | CHIP-BASED THERMO-STACK - A chip unit has a stack of at least two electronic chips stacked one on top of the other, a through-chip connection within the stack, the through-chip connection including a bounding material having an inner and outer perimeter, the inner perimeter defining an interior volume longitudinally extending through at least one of the at least two chips and at least partially into another of the at least two chips so as to form a tube extending between the one and the other of the chips, and an amount of working fluid hermetically sealed within the tube, the working fluid having a volume and being at a pressure such that the working fluid and tube will operate as a heat pipe and transfer heat from the stack of chips to the working fluid. | 10-29-2009 |
| 20100055838 | SENSITIVITY CAPACITIVE SENSOR - A method of creating an improved sensitivity capacitive fingerprint sensor involves forming vias from a first side of a sensor chip having an array of capacitive sensors, making the vias electrically conductive, and attaching a cover plate over the first side of the sensor chip spaced from the sensor chip by a distance of less than 25 μm. An improved sensitivity capacitive fingerprint sensor has a capacitive sensor array including multiple sensor cells and electrically conductive, through-chip vias extending from connection points for sensor cell circuitry to a back side of the capacitive sensor array, a chip including active detection circuitry and electrical connection points, the electrical connection points being respectively connected to corresponding ones of the sensor cell circuitry connection points, and a cover plate, disposed above the sensor cells at a spacing of less than 25 μm. | 03-04-2010 |
| 20100140776 | TRIAXIAL THROUGH-CHIP CONNECTON - A method performed on a wafer having multiple chips each including a doped semiconductor and substrate involves etching an annulus trench, metalizing an inner and an outer perimeter side wall of the annulus trench, etching a via trench into the wafer, making a length of the via trench electrically conductive, thinning a surface of the substrate. | 06-10-2010 |
| 20100148343 | SIDE STACKING APPARATUS AND METHOD - A module has at least two ICs connected to each other such that they lie in different planes and are arranged as a first stack of ICs, a third IC is connected to at least one of the at least two ICs, wherein the third IC is off plane from both of the at least two ICs. | 06-17-2010 |
| 20100176844 | VARIABLE OFF-CHIP DRIVE - A driver circuit includes a set of selectable drivers each having an individual drive capability, the drivers being selectable such that i) when a subset of the drivers is selected, a signal will be driven by the drivers at a first drive level, and ii) when the subset of the drivers and at least one additional driver is selected, signal will be driven by the drivers at a level that is greater than the first level by a level of drive provided by the least one additional driver. | 07-15-2010 |
| 20100197134 | COAXIAL THROUGH CHIP CONNECTION - An integrated circuit chip includes devices formed by doping of a semiconductor on a substrate and at least one post-device formation through-chip via made up of an annulus of insulating material, an annulus of metallization bounding an outer surface of the annulus of insulating material and an annulus of electrically conductive material within the annulus of insulating material, the annulus of metallization and the annulus of electrically conductive material being electrically isolated from each another. | 08-05-2010 |
| 20100219503 | CHIP CAPACITIVE COUPLING - A method of creating a semiconductor chip having a substrate, a doped semiconductor material abutting the substrate and a device pad at an outer side of the doped semiconductor material involves creating a via through at least a portion of the substrate, the via having a periphery and a bottom at a location and depth sufficient to bring the via into proximity with the device pad but be physically spaced apart from the device pad, introducing an electrically conductive material into the via, and connecting the electrically conductive material to a signal source so the signal will deliberately be propagated from the electrically conductive material to the device pad without any direct electrical connection existing between the electrically conductive material and the device pad. | 09-02-2010 |
| 20100261297 | REMOTE CHIP ATTACHMENT - A method of attaching a pair of chips, each having primary contacts that can be mated to each other, involves forming one or more secondary contacts on each of the two chips of a shape sufficient to prevent an initial attachment material from contacting any of the primary contacts during a preliminary attachment operation, the secondary contacts further having a height that will prevent the primary contacts from touching when the secondary contacts are brought into contact with each other, bringing the secondary contacts into closer and closer aligned proximity to each other at least until the primary contacts touch in a first phase, and heating the primary contacts until material between each of corresponding primary contacts on each of the chips in the pair forms an electrical connection. | 10-14-2010 |
| 20110147932 | CONTACT-BASED ENCAPSULATION - An electrical connection between two chips includes an IC pad on a first chip, an IC pad on a second chip, a first barrier metal over the IC pad of the first chip, a second barrier metal over the IC pad of the second chip, a malleable electrically conductive metal, different from the barrier metals, trapped between the first barrier metal and the second barrier metal, the first barrier metal, the malleable conductive metal and the second barrier metal forming a complete electrically conductive path between the IC pad of the first chip and the IC pad of the second chip. | 06-23-2011 |
