Patent application number | Description | Published |
20090110092 | DATA PROCESSING APPARATUS AND METHOD - A data processing apparatus is arranged to map input data symbols to be communicated onto a predetermined number of sub-carrier signals of Orthogonal Frequency Division Multiplexed OFDM symbols. The predetermined number of sub-carrier signals is determined in accordance with one of a plurality of operating modes and the input data symbols are divided into first sets of input data symbols and second sets of input data symbols. The data processing apparatus comprises an interleaver operable to perform an odd interleaving process which interleaves the first sets of input data symbols on to the sub-carrier signals of first OFDM symbols and an even interleaving process which interleaves the second sets of input data symbols on to the sub-carrier signals of second OFDM symbols, such that while the input data symbols from the first set are being read from locations in the interleaver memory, input data symbols from the second set can be written to the locations just read from and when input data symbols from the second set are being read from the locations in the interleaver memory, the input data symbols from a following first set can be written to the locations just read from. Furthermore, when the modulation mode is a mode which includes half or less than half a number of sub-carrier signals than a total number of sub-carriers in the OFDM symbols for carrying the input data symbols that can be accommodated by the interleaver memory, the data processing apparatus is operable to interleave the input data symbols from both first and second sets in accordance with the odd interleaving process on to the first and second OFDM symbols. | 04-30-2009 |
20090110093 | DATA PROCESSING APPARATUS AND METHOD - A data processing apparatus maps input symbols to be communicated onto a predetermined number of sub-carrier signals of an Orthogonal Frequency Division Multiplexed (OFDM) symbol. The data processor includes an interleaver memory which reads-in the predetermined number of data symbols for mapping onto the OFDM sub-carrier signals. The interleaver memory reads-out the data symbols on to the OFDM sub-carriers to effect the mapping, the read-out being in a different order than the read-in, the order being determined from a set of addresses, with the effect that the data symbols are interleaved on to the sub-carrier signals. The set of addresses are generated from an address generator which comprises a linear feedback shift register and a permutation circuit. A generator polynomial for the linear feedback shift register of R′ | 04-30-2009 |
20090110094 | DATA PROCESSING APPARATUS AND METHOD - A data processing apparatus maps input symbols to be communicated onto a predetermined number of sub-carrier signals of an Orthogonal Frequency Division Multiplexed (OFDM) symbol. The data processor includes an interleaver memory which reads-in the predetermined number of data symbols for mapping onto the OFDM sub-carrier signals. The interleaver memory reads-out the data symbols on to the OFDM sub-carriers to effect the mapping, the read-out being in a different order than the read-in, the order being determined from a set of addresses, with the effect that the data symbols are interleaved on to the sub-carrier signals. The set of addresses are generated from an address generator which comprises a linear feedback shift register and a permutation circuit. The linear feedback shift register has twelve register stages with a generator polynomial for the linear feedback shift register of R′ | 04-30-2009 |
20090110095 | DATA PROCESSING APPARATUS AND METHOD - A data processor maps input symbols to be communicated onto a predetermined number of sub-carrier signals of an Orthogonal Frequency Division Multiplexed (OFDM) symbol. The data processor includes an interleaver memory which reads-in the predetermined number of data symbols for mapping onto the OFDM sub-carrier signals. The interleaver memory reads-out the data symbols on to the OFDM sub-carriers to effect the mapping, the read-out being in a different order than the read-in, the order being determined from a set of addresses, with the effect that the data symbols are interleaved on to the sub-carrier signals. The set of addresses are generated from an address generator which comprises a linear feedback shift register and a permutation circuit. A generator polynomial for the linear feedback shift register is R′ | 04-30-2009 |
20090110097 | DATA PROCESSING APPARATUS AND METHOD - A data processing apparatus maps input symbols to be communicated onto a predetermined number of sub-carrier signals of an Orthogonal Frequency Division Multiplexed (OFDM) symbol. The data processor includes an interleaver memory which reads-in the predetermined number of data symbols for mapping onto the OFDM sub-carrier signals. The interleaver memory reads-out the data symbols on to the OFDM sub-carriers to effect the mapping, the read-out being in a different order than the read-in, the order being determined from a set of addresses, with the effect that the data symbols are interleaved on to the sub-carrier signals. The set of addresses are generated from an address generator which comprises a linear feedback shift register and a permutation circuit. The linear feedback shift register has eleven register stages with a generator polynomial for the linear feedback shift register of R′ | 04-30-2009 |
20090110098 | DATA PROCESSING APPARATUS AND METHOD - A data processing apparatus maps input symbols to be communicated onto a predetermined number of sub-carrier signals of an Orthogonal Frequency Division Multiplexed (OFDM) symbol. The data processor includes an interleaver memory which reads-in the predetermined number of data symbols for mapping onto the OFDM sub-carrier signals. The interleaver memory reads-out the data symbols on to the OFDM sub-carriers to effect the mapping, the read-out being in a different order than the read-in, the order being determined from a set of addresses, with the effect that the data symbols are interleaved on to the sub-carrier signals. The set of addresses are generated from an address generator which comprises a linear feedback shift register and a permutation circuit. The linear feedback shift register has ten register stages with a generator polynomial for the linear feedback shift register of R′ | 04-30-2009 |
20120069922 | DATA PROCESSING APPARATUS AND METHOD - A data processing apparatus maps input symbols to be communicated onto a predetermined number of sub-carrier signals of an Orthogonal Frequency Division Multiplexed (OFDM) symbol. The data processor includes an interleaver memory which reads-in the predetermined number of data symbols for mapping onto the OFDM sub-carrier signals. The interleaver memory reads-out the data symbols on to the OFDM sub-carriers to effect the mapping, the read-out being in a different order than the read-in, the order being determined from a set of addresses, with the effect that the data symbols are interleaved on to the sub-carrier signals. The set of addresses are generated from an address generator which comprises a linear feedback shift register and a permutation circuit. | 03-22-2012 |
20120099665 | DATA PROCESSING APPARATUS AND METHOD - A data processor maps input symbols to be communicated onto a predetermined number of sub-carrier signals of an Orthogonal Frequency Division Multiplexed (OFDM) symbol. The data processor includes an interleaver memory which reads-in the predetermined number of data symbols for mapping onto the OFDM sub-carrier signals. The interleaver memory reads-out the data symbols on to the OFDM sub-carriers to effect the mapping, the read-out being in a different order than the read-in, the order being determined from a set of addresses, with the effect that the data symbols are interleaved on to the sub-carrier signals. The set of addresses are generated from an address generator which comprises a linear feedback shift register and a permutation circuit. | 04-26-2012 |
20120106673 | ODD INTERLEAVING ONLY OF AN ODD-EVEN INTERLEAVER WHEN HALF OR LESS DATA SUBCARRIERS ARE ACTIVE IN A DIGITAL VIDEO BROADCASTING (DVB) SYSTEM - A data processing apparatus is arranged to map input data symbols to be communicated onto a predetermined number of sub-carrier signals of Orthogonal Frequency Division Multiplexed OFDM symbols. The predetermined number of sub-carrier signals is determined in accordance with one of a plurality of operating modes and the input data symbols are divided into first sets of input data symbols and second sets of input data symbols. The data processing apparatus comprises an interleaver operable to perform an odd interleaving process which interleaves the first sets of input data symbols on to the sub-carrier signals of first OFDM symbols and an even interleaving process which interleaves the second sets of input data symbols on to the sub-carrier signals of second OFDM symbols. | 05-03-2012 |
20120127372 | 2K MODE INTERLEAVER WITH ODD INTERLEAVING ONLY AND PER OFDM SYMBOL PERMUTAION CODE CHANGE IN A DIGITAL VIDEO BROADCASTING (DVB) STANDARD - A data processing apparatus maps input symbols to be communicated onto a predetermined number of sub-carrier signals of an Orthogonal Frequency Division Multiplexed (OFDM) symbol. The data processor includes an interleaver memory which reads-in the predetermined number of data symbols for mapping onto the OFDM sub-carrier signals. The interleaver memory reads-out the data symbols on to the OFDM sub-carriers to effect the mapping, the read-out being in a different order than the read-in, the order being determined from a set of addresses, with the effect that the data symbols are interleaved on to the sub-carrier signals. The set of addresses are generated from an address generator which comprises a linear feedback shift register and a permutation circuit. | 05-24-2012 |
20120134431 | 8K MODE INTERLEAVER WITH ODD INTERLEAVING ONLY AND PER OFDM SYMBOL PERMUTATION CODE CHANGE IN A DIGITAL VIDEO BROADCASTING (DVB) STANDARD - A data processing apparatus maps input symbols to be communicated onto a predetermined number of sub-carrier signals of an Orthogonal Frequency Division Multiplexed (OFDM) symbol. The data processor includes an interleaver memory which reads-in the predetermined number of data symbols for mapping onto the OFDM sub-carrier signals. The interleaver memory reads-out the data symbols on to the OFDM sub-carriers to effect the mapping, the read-out being in a different order than the read-in, the order being determined from a set of addresses, with the effect that the data symbols are interleaved on to the sub-carrier signals. The set of addresses are generated from an address generator which comprises a linear feedback shift register and a permutation circuit. | 05-31-2012 |
20120147981 | 4K MODE INTERLEAVER WITH ODD INTERLEAVING ONLY AND PER OFDM SYMBOL PERMUTATION CODE CHANGE IN A DIGITAL VIDEO BROADCASTING (DVB) STANDARD - A data processing apparatus maps input symbols to be communicated onto a predetermined number of sub-carrier signals of an Orthogonal Frequency Division Multiplexed (OFDM) symbol. The data processor includes an interleaver memory which reads-in the predetermined number of data symbols for mapping onto the OFDM sub-carrier signals. The interleaver memory reads-out the data symbols on to the OFDM sub-carriers to effect the mapping, the read-out being in a different order than the read-in, the order being determined from a set of addresses, with the effect that the data symbols are interleaved on to the sub-carrier signals. The set of addresses are generated from an address generator which comprises a linear feedback shift register and a permutation circuit. The linear feedback shift register has eleven register stages with a generator polynomial for the linear feedback shift register of R | 06-14-2012 |
20120212665 | SIGNAL ACQUISITION APPARATUS AND METHOD AND SIGNAL TRANSMISSION APPARATUS AND METHOD - A receiver comprises a first signal acquisition unit for acquiring a first type of signal block formatted according to a first format, the first signal acquisition unit comprising one or more parameter estimation units for estimating from the received signals one or more signal parameters related to acquisition of the first type of signal block, and wherein where the first type of signal block is interleaved with a second type of signal block formatted according to a second format, one or more parameter estimation units are arranged in operation to conduct signal parameter estimation based upon one or more respective properties of the received second type of signal block prior to continuation of the estimation based upon one or more respective properties of the received first type of signal block. | 08-23-2012 |
20120250777 | DATA PROCESSING APPARATUS AND METHOD - A data processing apparatus maps input symbols to be communicated onto a predetermined number of sub-carrier signals of an Orthogonal Frequency Division Multiplexed (OFDM) symbol. The data processor includes an interleaver memory which reads-in the predetermined number of data symbols for mapping onto the OFDM sub-carrier signals. The interleaver memory reads-out the data symbols on to the OFDM sub-carriers to effect the mapping, the read-out being in a different order than the read-in, the order being determined from a set of addresses, with the effect that the data symbols are interleaved on to the sub-carrier signals. The set of addresses are generated from an address generator which comprises a linear feedback shift register and a permutation circuit. | 10-04-2012 |
20130003758 | DATA PROCESSING APPARATUS AND METHOD FOR USE IN A 0.5K MODE INTERLEAVER IN A DIGITAL VIDEO BROADCASTING STANDARD INCLUDING DVB-TERRESTRIAL2 - A data processing apparatus maps input symbols to be communicated onto a predetermined number of sub-carrier signals of an Orthogonal Frequency Division Multiplexed (OFDM) symbol. The data processor includes an interleaver memory which reads-in the predetermined number of data symbols for mapping onto the OFDM sub-carrier signals. The interleaver memory reads-out the data symbols on to the OFDM sub-carriers to effect the mapping, the read-out being in a different order than the read-in, the order being determined from a set of addresses, with the effect that the data symbols are interleaved on to the sub-carrier signals. The set of addresses are generated from an address generator which comprises a linear feedback shift register and a permutation circuit. | 01-03-2013 |
20130114760 | DATA PROCESSING APPARATUS AND METHOD FOR INTERLEAVING AND DEINTERLEAVING DATA - A data processing apparatus is arranged to map input data symbols to be communicated onto a predetermined number of sub-carrier signals of Orthogonal Frequency Division Multiplexed OFDM symbols. The predetermined number of sub-carrier signals is determined in accordance with one of a plurality of operating modes and the input data symbols are divided into first sets of input data symbols and second sets of input data symbols. | 05-09-2013 |
20130314607 | TELEVISION RECEIVER, TELEVISION CONTROLLER CIRCUITRY AND METHOD - A television receiver for receiving TV signals when unknown interference is present in a predetermined bandwidth in which the TV signals are transmitted. The TV receiver comprises an input, a tuner, a configurable filter and a controller circuitry. The input receives a radio frequency (RF) signal comprising the terrestrial TV signals. The tuner is configured to detect the terrestrial TV signals, where the terrestrial TV signals include a plurality of frequency channels within a predetermined bandwidth and the plurality of frequency channels provide TV signals which communicate TV channels. The configurable filter is configurable to suppress signals received from one or more of the plurality of frequency channels within the predetermined bandwidth. The controller circuitry is operable to form a channel map of the TV channels detected by the tuner for selection by a user of the television set and consequent upon a TV channel not being detected on a frequency channel, configure the frequency domain filter to suppress signals received from the frequency channel. | 11-28-2013 |
20140072081 | DATA PROCESSING APPARATUS AND METHOD FOR USE IN AN INTERLEAVER SUITABLE FOR MULTIPLE OPERATING MODES - A data processing apparatus maps input symbols to be communicated onto a predetermined number of sub-carrier signals of an Orthogonal Frequency Division Multiplexed (OFDM) symbol. The data processor includes an interleaver memory which reads-in the predetermined number of data symbols for mapping onto the OFDM sub-carrier signals. The interleaver memory reads-out the data symbols on to the OFDM sub-carriers to effect the mapping, the read-out being in a different order than the read-in, the order being determined from a set of addresses, with the effect that the data symbols are interleaved on to the sub-carrier signals. The set of addresses are generated from an address generator which comprises a linear feedback shift register and a permutation circuit. | 03-13-2014 |
20140085544 | TELEVISION RECEIVER, TELEVISION CONTROLLER CIRCUITRY AND METHOD - A television receiver for receiving TV signals when unknown interference is present in a predetermined bandwidth in which the TV signals are transmitted. The TV receiver comprises an input, a tuner, a configurable filter and a controller circuitry. The input receives a radio frequency (RF) signal comprising the terrestrial TV signals. The tuner is configured to detect the terrestrial TV signals, where the terrestrial TV signals include a plurality of frequency channels within a predetermined bandwidth and the plurality of frequency channels provide TV signals which communicate TV channels. The configurable filter is configurable to suppress signals received from one or more of the plurality of frequency channels within the predetermined bandwidth. The controller circuitry is operable to form a channel map of the TV channels detected by the tuner for selection by a user of the television set and consequent upon a TV channel not being detected on a frequency channel, configure the frequency domain filter to suppress signals received from the frequency channel. | 03-27-2014 |
20140233681 | DATA PROCESSING APPARATUS AND METHOD FOR INTERLEAVING AND DEINTERLEAVING DATA - A data processing apparatus is arranged to map input data symbols to be communicated onto a predetermined number of sub-carrier signals of Orthogonal Frequency Division Multiplexed OFDM symbols. The predetermined number of sub-carrier signals is determined in accordance with one of a plurality of operating modes and the input data symbols are divided into first sets of input data symbols and second sets of input data symbols. | 08-21-2014 |
20150049838 | DATA PROCESSING APPARATUS AND METHOD FOR USE IN AN INTERLEAVER SUITABLE FOR MULTIPLE OPERATING MODES - A data processing apparatus maps input symbols to be communicated onto a predetermined number of sub-carrier signals of an Orthogonal Frequency Division Multiplexed (OFDM) symbol. The data processor includes an interleaver memory which reads-in the predetermined number of data symbols for mapping onto the OFDM sub-carrier signals. The interleaver memory reads-out the data symbols on to the OFDM sub-carriers to effect the mapping, the read-out being in a different order than the read-in, the order being determined from a set of addresses, with the effect that the data symbols are interleaved on to the sub-carrier signals. The set of addresses are generated from an address generator which comprises a linear feedback shift register and a permutation circuit. | 02-19-2015 |
20150063489 | DATA PROCESSING APPARATUS AND METHOD FOR INTERLEAVING AND DEINTERLEAVING DATA - A data processing apparatus is arranged to map input data symbols to be communicated onto a predetermined number of sub-carrier signals of Orthogonal Frequency Division Multiplexed OFDM symbols. The predetermined number of sub-carrier signals is determined in accordance with one of a plurality of operating modes and the input data symbols are divided into first sets of input data symbols and second sets of input data symbols. | 03-05-2015 |