| Patent application number | Description | Published |
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| 20080201495 | HANDLING DMA OPERATIONS DURING A PAGE COPY - A memory controller provides page copy logic that assures data coherency when a DMA operation to a page occurs during the copying of the page by the memory controller. The page copy logic compares the page index of the DMA operation to a copy address pointer that indicates the location currently being copied. If the page index of the DMA operation is less than the copy address pointer, the portion of the page that would be written to by the DMA operation has already been copied, so the DMA operation is performed to the physical address of the new page. If the page index of the DMA operation is greater than the copy address pointer, the portion of the page that would be written to by the DMA operation has not yet been copied, so the DMA operation is performed to the physical address of the old page. | 08-21-2008 |
| 20080244112 | HANDLING DMA REQUESTS IN A VIRTUAL MEMORY ENVIRONMENT - An apparatus includes a virtual memory manager that moves data from a first block to second block in memory. When the virtual memory manager is ready to transfer data from the first block to the second block, a third, temporary block of memory is defined. The translation table in a DMA controller is changed to point DMA transfers that target the first block to instead target the temporary block. The virtual memory manager then transfers data from the first block to the second block. When the transfer is complete, a check is made to see if the DMA transferred data to the temporary block while the data from the first block was being written to the second block. If so, the data written to the temporary block is written to the second block. A hardware register is preferably used to efficiently detect changes to the temporary block. | 10-02-2008 |
| 20080307252 | Method and Apparatus for Implementing Redundant Memory Access Using Multiple Controllers on the Same Bank of Memory - A method and apparatus implement redundant memory access using multiple controllers on the same bank of memory. A first memory controller uses the memory as its primary address space, for storage and fetches. A second redundant controller is also connected to the same memory. System control logic is used to notify the redundant controller of the need to take over the memory interface. The redundant controller initializes if required and takes control of the memory. The memory only needs to be initialized if the system has to be brought down and restarted in the redundant mode. This invention allows the system to continue to stay up and continue running during a memory controller or link failure. | 12-11-2008 |
| 20080307253 | Method and Apparatus for Implementing Redundant Memory Access Using Multiple Controllers on the Same Bank of Memory - A method and apparatus implement redundant memory access using multiple controllers on the same bank of memory, and a design structure on which the subject circuit resides is provided. A first memory controller uses the memory as its primary address space, for storage and fetches. A second redundant controller is also connected to the same memory. System control logic is used to notify the redundant controller of the need to take over the memory interface. The redundant controller initializes if required and takes control of the memory. The memory only needs to be initialized if the system has to be brought down and restarted in the redundant mode. This invention allows the system to continue to stay up and continue running during a memory controller or link failure. | 12-11-2008 |
| 20090006705 | Hub for Supporting High Capacity Memory Subsystem - A high-capacity memory subsystem architecture utilizes multiple memory modules arranged in one or more clusters, each attached to a respective hub which in turn is attached to a memory controller. Within a cluster, data is interleaved so that each data access command accesses all modules of the cluster. The hub communicates with the memory modules at a lower bus frequency, but the distributing of data among multiple modules enables the cluster to maintain the composite data rate of the memory-controller-to-hub bus. Preferably, the memory system employs buffered memory chips having dual-mode operation, one of which supports a cluster configuration in which data is interleaved and the communications buses operate at reduced bus width and/or reduced bus frequency to match the level of interleaving | 01-01-2009 |
| 20090006715 | Memory Chip for High Capacity Memory Subsystem Supporting Multiple Speed Bus - A memory module contains an interface for receiving memory access commands from an external source, in which a first portion of the interface receives memory access data at a first bus frequency and a second portion of the interface receives memory access data at a second different bus frequency. Preferably, the memory module contains a second interface for re-transmitting memory access data, also operating at dual frequency. The memory module is preferably used in a high-capacity memory subsystem organized in a tree configuration in which data accesses are interleaved. Preferably, the memory module has multiple-mode operation, one of which supports dual-speed buses for receiving and re-transmitting different parts of data access commands, and another of which supports conventional daisy-chaining. | 01-01-2009 |
| 20090006752 | High Capacity Memory Subsystem Architecture Employing Hierarchical Tree Configuration of Memory Modules - A high-capacity memory subsystem architecture utilizes multiple memory modules arranged in a hierarchical tree configuration, in which at least some communications from an external source traverse successive levels of the tree to reach memory modules at the lowest level. Preferably, the memory system employs buffered memory chips having dual-mode operation, one of which supports a tree configuration in which data is interleaved and the communications buses operate at reduced bus width and/or reduced bus frequency to match the level of interleaving | 01-01-2009 |
| 20090006772 | Memory Chip for High Capacity Memory Subsystem Supporting Replication of Command Data - A memory module contains a first interface for receiving data access commands and a second interface for re-transmitting data access commands to other memory modules, the second interface propagating multiple copies of received data access commands to multiple other memory modules. The memory module is preferably used in a high-capacity memory subsystem organized in a tree configuration in which data accesses are interleaved. Preferably, the memory module has multiple-mode operation, one of which supports multiple replication of commands and another of which supports conventional daisy-chaining | 01-01-2009 |
| 20090006774 | High Capacity Memory Subsystem Architecture Employing Multiple-Speed Bus - A high-capacity memory subsystem architecture utilizes multiple memory modules coupled to one or more access modules by a communications medium, in which at least some data is transferred between an access module and memory modules at a first bus frequency, and at least some data is transferred between the access module and memory modules at a second bus frequency different from the first. Preferably, data is interleaved to reduce the required bus speed for read/write data, and the higher bus frequency is used to transfer command/address data. Preferably, the memory system employs memory chips having dual-mode operation, one of which supports a dual-speed bus. | 01-01-2009 |
| 20090006775 | Dual-Mode Memory Chip for High Capacity Memory Subsystem - A dual-mode memory chip supports a first operation mode in which received data access commands contain chip select data to identify the chip addressed by the command, and control logic in the memory chip determines whether the command is addressed to the chip, and a second operation mode in which the received data access command addresses a set of multiple chips. Preferably, the first mode supports a daisy-chained configuration of memory chips. Preferably the second mode supports a hierarchical interleaved memory subsystem, in which each addressable set of chips is configured as a tree, command and write data being propagated down the tree, the number of chips increasing at each succeeding level of the tree. | 01-01-2009 |
| 20090006790 | High Capacity Memory Subsystem Architecture Storing Interleaved Data for Reduced Bus Speed - A high-capacity memory subsystem architecture utilizes multiple memory modules arranged in one or more clusters, each attached to a respective hub which in turn is attached to a memory controller. Within a cluster, data is interleaved so that each data access command accesses all modules of the cluster. The hub communicates with the memory modules at a lower bus frequency, but the distributing of data among multiple modules enables the cluster to maintain the composite data rate of the memory-controller-to-hub bus. Preferably, the memory system employs buffered memory chips having dual-mode operation, one of which supports a cluster configuration in which data is interleaved and the communications buses operate at reduced bus width and/or reduced bus frequency to match the level of interleaving | 01-01-2009 |
| 20090073739 | DYNAMIC RECONFIGURATION OF SOLID STATE MEMORY DEVICE TO REPLICATE AND TIME MULTIPLEX DATA OVER MULTIPLE DATA INTERFACES - Multiple interfaces dedicated to individual logic circuits such as memory arrays are capable of being dynamically reconfigured from operating separately and in parallel to operating in a more collective manner to ensure that data associated with all of the logic circuits will be communicated irrespective of a failure in any of the interfaces. Specifically, a plurality of interfaces, each of which being ordinarily configured to communicate data associated with an associated logic circuit in parallel with the other interfaces, may be dynamically reconfigured, e.g., in response to a detected failure in one or more of the interfaces, to communicate data associated with each of the interfaces over each of at least a subset of the interfaces in a time multiplexed and replicated manner. | 03-19-2009 |
| 20090164990 | Apparatus for and Method for Real-Time Optimization of virtual Machine Input/Output Performance - The present invention implements a mechanism to decide when it is beneficial to switch from the current virtual input/output mechanism to a different one. The present invention determines which input/output mechanism each virtual machine should use based on the available input/output resources of the virtual machines (with their respective available input/output adapters), the number of virtual machines running and their input/output needs, and the input/output needs of the virtual machine being considered. The present invention also provides a mechanism for virtual machine to seamlessly switch input/output mechanisms. When beneficial, the standard hot-plug mechanism of the virtual machine and the hypervisor is used to first remove the existing input/output mechanism and then add the new input/output mechanism. | 06-25-2009 |
| 20090300291 | Implementing Cache Coherency and Reduced Latency Using Multiple Controllers for Memory System - A method and apparatus implement cache coherency and reduced latency using multiple controllers for a memory system, and a design structure is provided on which the subject circuit resides. A first memory controller uses a first memory as its primary address space, for storage and fetches. A second memory controller is also connected to the first memory. A second memory controller uses a second memory as its primary address space, for storage and fetches. The first memory controller is also connected to the second memory. The first memory controller and the second memory controller, for example, are connected together by a processor communications bus. A request and send sequence of the invention sends data directly to a requesting memory controller eliminating the need to re-route data back through a responding controller, and improving the latency of the data transfer. | 12-03-2009 |
| 20090300411 | Implementing Redundant Memory Access Using Multiple Controllers for Memory System - A method and apparatus implement redundant memory access using multiple controllers for a memory system, and a design structure on which the subject circuit resides are provided. A first memory controller uses a first memory and a second memory controller uses the second memory as its respective primary address space, for storage and fetches. The second memory controller is also connected to the first memory. The first memory controller is also connected to the second memory. The first memory controller and the second memory controller, for example, are connected together by a processor communications bus. When one of the first memory controller or the second memory controller fails, then the other memory controller is notified. The other memory controller takes control of the memory for the failed controller, using the direct connection to that memory, and maintains coherence of both the first memory and second memory. | 12-03-2009 |
| 20100191894 | Digital Data Architecture Employing Redundant Links in a Daisy Chain of Component Modules - A communications architecture utilizes modules arranged in a daisy-chain, each module supporting multiple input and output ports. Point-to-point links are arranged so that a first output link of each of multiple modules connects to the next module in the chain, and a second output link connects to a module after it, and inputs arranged similarly, so that any single module can be by-passed in the event of malfunction. Multiple chains may be cross-linked and/or serviced by hubs or chains of hubs. Preferably, the redundant links are used in a non-degraded operating mode to provide higher bandwidth and/or reduced latency of communication. The exemplary embodiment is a memory subsystem in which the modules are buffered memory chips. | 07-29-2010 |
