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John M. Safran

John M. Safran, Hopewell Junction, NY US

Patent application numberDescriptionPublished
20100327399ELECTRICALLY PROGRAMMABLE FUSE USING ANISOMETRIC CONTACTS AND FABRICATION METHOD - An electrically programmable fuse that includes an anode contact region and a cathode contact region are formed of a polysilicon layer having a silicide layer formed thereon, and a fuse link conductively connecting the cathode contact region with the anode contact region, which is programmable by applying a programming current, and a plurality of anisometric contacts formed on the silicide layer of the cathode contact region or on both the silicide layer of the cathode contact region and the anode contact region in a predetermined configuration, respectively.12-30-2010

John M. Safran, Wappingers Falls, NY US

Patent application numberDescriptionPublished
20080217658ELECTRICAL ANTIFUSE WITH INTEGRATED SENSOR - The present invention provides structures for antifuses that utilize electromigration for programming. By providing a portion of antifuse link with high resistance without conducting material and then by inducing electromigration of the conducting material into the antifuse link, the resistance of the antifuse structure is changed. By providing a terminal on the antifuse link, the change in the electrical properties of the antifuse link is detected and sensed. Also disclosed are an integrated antifuse with a built-in sensing device and a two dimensional array of integrated antifuses that can share programming transistors and sensing circuitry.09-11-2008
20080217736ELECTRICAL ANTIFUSE, METHOD OF MANUFACTURE AND METHOD OF PROGRAMMING - An antifuse having a link including a region of unsilicided semiconductor material may be programmed at reduced voltage and current and with reduced generation of heat by electromigration of metal or silicide from a cathode into the region of unsilicided semiconductor material to form an alloy having reduced bulk resistance. The cathode and anode are preferably shaped to control regions from which and to which material is electrically migrated. After programming, additional electromigration of material can return the antifuse to a high resistance state. The process by which the antifuse is fabricated is completely compatible with fabrication of field effect transistors and the antifuse may be advantageously formed on isolation structures.09-11-2008
20080218247METHOD FOR AUTOMATICALLY ADJUSTING ELECTRICAL FUSE PROGRAMMING VOLTAGE - The present invention provides a circuit for determining the optimal gate voltage for programming transistors. The determination of the optimal voltage compensates for the variations in the programming current due to process variations in manufacturing or due to ambient conditions. By applying the optimal gate voltage thus determined to the programming transistors of electrical fuses, the optimal level of current is passed through the electrical fuses to enable high yielding and reliable electrical fuse programming.09-11-2008
20080316789Random Access Electrically Programmable E-Fuse Rom - A one-time-programmable-read-only-memory (OTPROM) is implemented in a two-dimensional array of aggressively scaled suicide migratable e-fuses. Word line selection is performed by decoding logic operating at V12-25-2008
20090114971CMOS EPROM AND EEPROM DEVICES AND PROGRAMMABLE CMOS INVERTERS - A CMOS EPROM, EEPROM or inverter device includes an nFET device with a thin gate dielectric layer and a pFET device juxtaposed with the nFET device with a thick gate dielectric layer and a floating gate electrode. The thick gate dielectric layer is substantially thicker than the thin gate dielectric layer. A common drain node connected both FET devices has no external connection in the case of a memory device and has an external connection in the case of an inverter. There are external circuit connections to the source regions of both FET devices and to the gate electrode of the nFET device. The pFET and nFET devices can be planar, vertical or FinFET devices.05-07-2009
20090141533METAL GATE COMPATIBLE ELECTRICAL ANTIFUSE - A metal layer and a semiconductor layer are sequentially deposited on a substrate. The semiconductor layer and the metal layer are lithographically patterned to form a stack of a semiconductor portion and a metal gate portion, which is preferably performed concurrently with formation of at least one metal gate stack. In one embodiment, the size of the semiconductor portion is reduced and a metal semiconductor alloy portion is formed on the semiconductor portion by metallization. In a first electrical antifuse formed thereby, the metal semiconductor alloy portion may be electromigrated to form a short between the metal semiconductor alloy portion and the metal gate portion. In another embodiment, two disjoined metal semiconductor alloy portions are formed on the semiconductor portion. In a second electrical antifuse formed thereby, the metal semiconductor alloy portion may be electromigrated to form a short between the two previously disjoined metal semiconductor alloy portions.06-04-2009
20090321735Electrical Antifuse and Method of Programming - An antifuse having a link including a region of unsilicided semiconductor material may be programmed at reduced voltage and current and with reduced generation of heat by electromigration of metal or silicide from a cathode into the region of unsilicided semiconductor material to form an alloy having reduced bulk resistance. The cathode and anode are preferably shaped to control regions from which and to which material is electrically migrated. After programming, additional electromigration of material can return the antifuse to a high resistance state. The process by which the antifuse is fabricated is completely compatible with fabrication of field effect transistors and the antifuse may be advantageously formed on isolation structures.12-31-2009

Patent applications by John M. Safran, Wappingers Falls, NY US