| Patent application number | Description | Published |
|---|
| 20080278125 | APPARATUS FOR OPTIMIZING DIODE CONDUCTION TIME DURING A DEADTIME INTERVAL - Deadtime optimization techniques and circuits are provided which implement closed loop feedback to reduce a duration of a deadtime interval by reducing a diode conduction time (DCT) to an optimized or minimized value. Information regarding DCT is fed back to continuously adjust the relative delay between a first driver path which drives a first transistor and a second driver path which drives a second transistor. For instance, information regarding DCT can be measured and stored, and then used to generate a control signal which continuously adjusts (e.g., increases or decreases) a variable delay associated with a delay element in one of the driver paths of one of the transistors. The delay is adjusted to a value which drives the DCT towards an optimum value. By continuously changing the relative delay between the first driver path and the second driver path, the DCT can be driven to an optimum value | 11-13-2008 |
| 20090079404 | SINGLE-INDUCTOR MULTIPLE-OUTPUT DC/DC CONVERTER METHOD - A method of configuring a DC/DC converter having a plurality of outputs for providing a regulated voltage to each output electrically coupled to an error amplifier of a plurality of error amplifiers and an inductor includes configuring a plurality of controllable switches coupled to the plurality of error amplifiers to operate using a plurality of duty cycles according to D | 03-26-2009 |
| 20090157929 | DATA ARBITRATION ON A BUS TO DETERMINE AN EXTREME VALUE - A system includes a master device and a plurality of slave devices. The master device initiates a bus transaction having an arbitration data field for processing by a subset of the slave devices. Each slave device of the subset arbitrates a corresponding data value for the arbitration data field via the multiple-access bus such that an extreme data value of the data values of the slave devices of the subset is transmitted via the multiple-access bus for the arbitration data field. The slave device can arbitrate its data value by providing the data value for serial transmission via a data line of the multiple-access bus and monitoring the data line. In response to determining that a bit value of the data value being provided does not match the state of the data line, the slave device terminates provision of the data value, thereby ceasing arbitration of its data value. | 06-18-2009 |
| 20090251117 | POWER CONVERTER WITH IMPROVED EFFICIENCY - A power converter ( | 10-08-2009 |
| 20100079126 | DUAL-LOOP DC-TO-DC CONVERTER APPARATUS - A dual loop DC-to-DC converter is provided that includes a first control loop that maintains a DC output voltage (V | 04-01-2010 |
| 20100102852 | CIRCUITS AND METHODS FOR BUFFERING AND COMMUNICATING DATA SIGNALS - Method and apparatus are provided for buffering a data signal to a low voltage logic device. A circuit for buffering the data signal to the low voltage logic device includes an output buffer and an N-type transistor. The output buffer has an input and an output, where the input is configured to receive the data signal. The output buffer is configured to produce an output signal based on the data signal, and the output signal has a maximum potential. The N-type transistor has a source coupled to the output, a drain configured to couple to the low voltage logic device, and a gate configured to receive a bias potential, where the bias potential is greater than the maximum potential. | 04-29-2010 |
| 20100164551 | SAMPLE-AND-HOLD (S/H) CIRCUIT - A sample-and-hold circuit ( | 07-01-2010 |
| 20100271078 | CIRCUITRY IN A DRIVER CIRCUIT - A driver circuit includes a first and a second voltage rail, a first pre-driver circuit, a power transistor, comparison circuitry which indicates when a voltage level of the first voltage rails is above or below a reference voltage level, a level shift circuit coupled between the first voltage rail and the second voltage rail which provides a level shifted output, a tapered buffer circuit coupled to the first voltage rail and to a first circuit node, wherein the tapered buffer circuit receives the level shifted output and provides a buffered output to a control electrode of the first pre-driver transistor, and a rail voltage adjusting circuit coupled between the first circuit node and the second voltage rail, which, in response to the comparison circuitry indicating that the voltage level of the first voltage rail is above the reference voltage level, adjusts a voltage level of the second voltage rail. | 10-28-2010 |
