| Patent application number | Description | Published |
|---|
| 20080232185 | Structure and Method of Implementing Power Savings During Addressing of DRAM Architectures - A random access memory device includes an array of individual memory cells arranged into rows and columns, each memory cell having an access device associated therewith. Each row of the array further includes a plurality of N word lines associated therewith, with a wherein N corresponds to a number of independently accessible partitions of the array, wherein each access device in a given row is coupled to only one of the N word lines of the row. Address decoder logic in signal communication with the array is configured to receive a plurality of row address bits and determine, for a requested row identified by the row address bits, which of the N partitions within the requested row are to be accessed, such that access devices within a selected row, but not within a partition to be accessed, are not activated. | 09-25-2008 |
| 20090006706 | Structure for Hub for Supporting High Capacity Memory Subsystem - A design structure is provided for a hub for use in a high-capacity memory subsystem in which memory modules arranged in one or more clusters, each attached to a respective hub which in turn is attached to a memory controller. Within a cluster, data is interleaved so that each data access command accesses all modules of the cluster. The hub communicates with the memory modules at a lower bus frequency, but the distributing of data among multiple modules enables the cluster to maintain the composite data rate of the memory-controller-to-hub bus. Preferably, the memory system employs buffered memory chips having dual-mode operation, one of which supports a cluster configuration in which data is interleaved and the communications buses operate at reduced bus width and/or reduced bus frequency to match the level of interleaving | 01-01-2009 |
| 20090006760 | Structure for Dual-Mode Memory Chip for High Capacity Memory Subsystem - A design structure is provided for a dual-mode memory chip supporting a first operation mode in which received data access commands contain chip select data to identify the chip addressed by the command, and control logic in the memory chip determines whether the command is addressed to the chip, and a second operation mode in which the received data access command addresses a set of multiple chips. Preferably, the first mode supports a daisy-chained configuration of memory chips. Preferably the second mode supports a hierarchical interleaved memory subsystem, in which each addressable set of chips is configured as a tree, command and write data being propagated down the tree, the number of chips increasing at each succeeding level of the tree. | 01-01-2009 |
| 20090006781 | Structure for Memory Chip for High Capacity Memory Subsystem Supporting Multiple Speed Bus - A design structure is provided for a memory module containing an interface for receiving memory access commands from an external source, in which a first portion of the interface receives memory access data at a first bus frequency and a second portion of the interface receives memory access data at a second different bus frequency. Preferably, the memory module contains a second interface for re-transmitting memory access data, also operating at dual frequency. The memory module is preferably used in a high-capacity memory subsystem organized in a tree configuration in which data accesses are interleaved. Preferably, the memory module has multiple-mode operation, one of which supports dual-speed buses for receiving and re-transmitting different parts of data access commands, and another of which supports conventional daisy-chaining. | 01-01-2009 |
| 20090006798 | Structure for Memory Chip for High Capacity Memory Subsystem Supporting Replication of Command Data - A design structure is provided for a memory module containing a first interface for receiving data access commands and a second interface for re-transmitting data access commands to other memory modules, the second interface propagating multiple copies of received data access commands to multiple other memory modules. The memory module is preferably used in a high-capacity memory subsystem organized in a tree configuration in which data accesses are interleaved. Preferably, the memory module has multiple-mode operation, one of which supports multiple replication of commands and another of which supports conventional daisy-chaining | 01-01-2009 |
| 20090031067 | Spider Web Interconnect Topology Utilizing Multiple Port Connection - A data communications apparatus includes a central device and a plurality of communication devices. The central device includes a plurality of central port pairs, in which each central port pair includes an input port and an output port. The plurality of communication devices is arranged in a spoke and ring configuration, in which each communication device is part of a communication spoke. Each communication spoke is in communication with a different central port pair. Each communication device is also a part of a communication ring, so that each communication device in a selected communication ring belongs to a different communication spoke. | 01-29-2009 |
| 20090196118 | Design Structure Of Implementing Power Savings During Addressing Of DRAM Architectures - A design structure embodied in a machine readable medium used in a design process includes random access memory device having an array of individual memory cells arranged into rows and columns, each memory cell having an access device associated therewith. Each row of the array further includes a plurality of N word lines associated therewith, with a wherein N corresponds to a number of independently accessible partitions of the array, wherein each access device in a given row is coupled to only one of the N word lines of the row. Logic in signal communication with the array receives a plurality of row address bits and determine, for a requested row identified by the row address bits, which of the N partitions within the requested row are to be accessed, such that access devices within a selected row, but not within a partition to be accessed, are not activated. | 08-06-2009 |
| 20090217281 | Adaptable Redundant Bit Steering for DRAM Memory Failures - A method, computer program product and computer system for assigning computing resources in a computer system to solve multiple problems where tolerances to the problems are countable and have pre-set thresholds, and solutions to the problems share resources exclusively. The method, computer program product and system include counting the tolerances using at least one counter, assigning resources to solve a problem if the tolerance to the problem is higher than a first pre-set threshold, and reassigning resources to solve a second problem if the tolerance to the second problem is higher than a second pre-set threshold. The method, computer program product and system can also adopt an alternative solution that does not share resources exclusively with a current solution to solve the problems. | 08-27-2009 |
| 20090249093 | Design Structure for Selecting Processors for Job Scheduling Using Measured Power Consumption - In a design structure for allocating a plurality of parts of a computational system to a computational job, a set of requirements necessary to execute the job is determined. A set of parts of the plurality of parts is assembled so that the set of parts is capable of meeting the set of requirements and so that a part is added to the set of parts based on a determination that the addition of the part will minimize power consumption by the set of parts. The set of parts are caused to execute the job. | 10-01-2009 |
