| Patent application number | Description | Published |
|---|
| 20080265340 | DISPOSABLE PILLARS FOR CONTACT FORMATION - Sacrificial plugs for forming contacts in integrated circuits, as well as methods of forming connections in integrated circuit arrays are disclosed. Various pattern transfer and etching steps can be used to create densely-packed features and the connections between features. A sacrificial material can be patterned in a continuous zig-zag line pattern that crosses word lines. Planarization can create parallelogram-shaped blocks of material that can overlie active areas to form sacrificial plugs, which can be replaced with conductive material to form contacts. | 10-30-2008 |
| 20090273051 | METHODS OF FORMING ISOLATED ACTIVE AREAS, TRENCHES, AND CONDUCTIVE LINES IN SEMICONDUCTOR STRUCTURES AND SEMICONDUCTOR STRUCTURES INCLUDING THE SAME - Methods of pitch doubling of asymmetric features and semiconductor structures including the same are disclosed. In one embodiment, a single photolithography mask may be used to pitch double three features, for example, of a DRAM array. In one embodiment, two wordlines and a grounded gate over field may be pitch doubled. Semiconductor structures including such features are also disclosed. | 11-05-2009 |
| 20110101298 | METHODS, STRUCTURES AND DEVICES FOR INCREASING MEMORY DENSITY - Non-volatile memory devices comprising a memory string including a plurality of vertically superimposed diodes. Each of the diodes may be arranged at different locations along a length of the electrode and may be spaced apart from adjacent diodes by a dielectric material. The electrode may electrically couple the diodes of the memory strings to one another and to another memory device, such as, a MOSFET device. Methods of forming the non-volatile memory devices as well as intermediate structures are also disclosed. | 05-05-2011 |
| 20110215396 | SEMICONDUCTOR CELLS, ARRAYS, DEVICES AND SYSTEMS HAVING A BURIED CONDUCTIVE LINE AND METHODS FOR FORMING THE SAME - Semiconductor arrays including a plurality of access devices disposed on a buried conductive line and methods for forming the same are provided. The access devices each include a transistor having a source region and drain region spaced apart by a channel region of opposite dopant type and an access line associated with the transistor. The access line may be electrically coupled with one or more of the transistors and may be operably coupled to a voltage source. The access devices may be formed in an array on one or more conductive lines. A system may be formed by integrating the semiconductor devices with one or more memory semiconductor arrays or conventional logic devices, such as a complementary metal-oxide-semiconductor (CMOS) device. | 09-08-2011 |
| 20110215407 | SEMICONDUCTOR-METAL-ON-INSULATOR STRUCTURES, METHODS OF FORMING SUCH STRUCTURES, AND SEMICONDUCTOR DEVICES INCLUDING SUCH STRUCTURES - Methods for fabricating semiconductor-metal-on-insulator (SMOI) structures include forming an acceptor wafer including an insulator material on a first semiconductor substrate, forming a donor wafer including a conductive material and an amorphous silicon material on a second semiconductor substrate, and bonding the amorphous silicon material of the donor wafer to the insulator material of the acceptor wafer. SMOI structures formed from such methods are also disclosed, as are semiconductor devices including such SMOI structures. | 09-08-2011 |
| 20110215408 | FLOATING BODY CELL STRUCTURES, DEVICES INCLUDING SAME, AND METHODS FOR FORMING SAME - Floating body cell structures including an array of floating body cells disposed on a back gate and source regions and drain regions of the floating body cells spaced apart from the back gate. The floating body cells may each include a volume of semiconductive material having a channel region extending between pillars, which may be separated by a void, such as a U-shaped trench. The floating body cells of the array may be electrically coupled to another gate, which may be disposed on sidewalls of the volume of semiconductive material or within the void therein. Methods of forming the floating body cell devices are also disclosed. | 09-08-2011 |
| 20110266647 | Methods of Forming Isolated Active Areas, Trenches, and Conductive Lines in Semiconductor Structures and Semiconductor Structures Including the Same - Methods of pitch doubling of asymmetric features and semiconductor structures including the same are disclosed. In one embodiment, a single photolithography mask may be used to pitch double three features, for example, of a DRAM array. In one embodiment, two wordlines and a grounded gate over field may be pitch doubled. Semiconductor structures including such features are also disclosed. | 11-03-2011 |
| 20110316042 | THYRISTOR RANDOM ACCESS MEMORY DEVICE AND METHOD - Memory devices and methods of making memory devices are shown. Methods and configurations as shown provide folded and vertical memory devices for increased memory density. Methods provided reduce a need for manufacturing methods such as deep dopant implants. | 12-29-2011 |
| 20110316063 | THREE DIMENSIONAL MEMORY AND METHODS OF FORMING THE SAME - Some embodiments include a memory device and methods of forming the memory device. One such memory device includes a first group of memory cells, each of the memory cells of the first group being formed in a cavity of a first control gate located in one device level of the memory device. The memory device also includes a second group of memory cells, each of the memory cells of the second group being formed in a cavity of a second control gate located in another device level of the memory device. Additional apparatus and methods are described. | 12-29-2011 |
