| Patent application number | Description | Published |
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| 20080229577 | Seek-scan probe (SSP) memory with sharp probe tips formed at CMOS-compatible temperatures - Embodiments of a process comprising forming one or more micro-electro-mechanical (MEMS) probe on a conductive metal oxide semiconductor (CMOS) wafer, wherein each MEMS probe comprises a cantilever beam with a fixed end and a free end and wherein the CMOS wafer has circuitry thereon; forming an unsharpened tip at or near the free end of each cantilever beam; depositing a silicide-forming material over the tip; annealing the wafer to sharpen the tip; and exposing the sharpened tip. Embodiments of an apparatus comprising a conductive metal oxide semiconductor (CMOS) wafer including circuitry therein; one or more micro-electro-mechanical (MEMS) probes integrally formed on the CMOS wafer, wherein each MEMS probe comprises a cantilever beam with a fixed end and a free end and a sharpened tip at or near the free end, the sharpened tip formed by a process comprising forming an unsharpened tip at or near the free end of each cantilever beam, depositing a silicide-forming material over the unsharpened tip, annealing the wafer to sharpen the unsharpened tip, and exposing the sharpened tip. | 09-25-2008 |
| 20080233672 | METHOD OF INTEGRATING MEMS STRUCTURES AND CMOS STRUCTURES USING OXIDE FUSION BONDING - A method to fabricate a device including a micro-electro-mechanical system structure and a monolithic integrated circuit comprises using a first wafer as a first substrate, fabricating the micro-electro-mechanical system structure on the first substrate, and forming a first oxide layer over the micro-electro-mechanical system structure. The method further comprises using a second wafer as a second substrate, fabricating the monolithic integrated circuit on the second substrate, and forming a second oxide layer over the monolithic integrated circuit. The first wafer and the second wafer are arranged so that the first oxide layer opposes the second oxide layer. The micro-electro-mechanical system structure is aligned with the monolithic integrated circuit, the first oxide layer is contacted with the second oxide layer; and bonded with the second oxide layer. | 09-25-2008 |
| 20080237003 | Inertial switch using fully released and enclosed conductive contact bridge - A micro-electromechanical system (MEMS) switch comprises a trench formed in a substrate. A free moving conductive mass may be formed within the cavity. When the switch is moved or otherwise acted upon my an inertial force to conductive mass makes contact with a pair of electrodes partially covering the trench thus turning the switch on. | 10-02-2008 |
| 20090001486 | Forming a cantilever assembly for verticle and lateral movement - In one embodiment, the present invention includes a method for forming a sacrificial oxide layer on a base layer of a microelectromechanical systems (MEMS) probe, patterning the sacrificial oxide layer to provide a first trench pattern having a substantially rectangular form and a second trench pattern having a substantially rectangular portion and a lateral portion extending from the substantially rectangular portion, and depositing a conductive layer on the patterned sacrificial oxide layer to fill the first and second trench patterns to form a support structure for the MEMS probe and a cantilever portion of the MEMS probe. Other embodiments are described and claimed. | 01-01-2009 |
| 20090294028 | PROCESS FOR FABRICATING HIGH DENSITY STORAGE DEVICE WITH HIGH-TEMPERATURE MEDIA - A method of fabricating an information storage device comprises providing a media substrate including a first side and a second side, forming a media on the first side of the media substrate, adhesively associating the media with a carrier substrate, thinning a surface of the second side of the media substrate while supporting and protecting the media with the carrier substrate, and forming circuitry on the thinned second side of the media substrate. | 12-03-2009 |
| 20100039729 | PACKAGE WITH INTEGRATED MAGNETS FOR ELECTROMAGNETICALLY-ACTUATED PROBE-STORAGE DEVICE - A packaged memory device for storing information comprises a stack, a package lid, a first magnet structure fixedly connected to the package lid, a package body and a second magnet structure connected with the package body. The stack includes a tip substrate, a cap, and a media arranged between the tip substrate and cap and movable relative to the tip substrate. The tip substrate includes a plurality of tips extending from the tip substrate so that the tips can access the media. The first magnet structure includes a first magnet connected with a first flux plate. The second magnet structure includes a second magnet connected with a second flux plate. The second flux plate is integrated with the package body so that the second flux plate provides structural rigidity to the package body. The stack is connected to one or both of the package body and the second magnet. | 02-18-2010 |
| 20100320606 | Method for Forming MEMS Devices Having Low Contact Resistance and Devices Obtained Thereof - The present disclosure proposes a method for manufacturing in a MEMS device a low-resistance contact between a silicon-germanium layer and a layer contacted by this silicon-germanium layer, such as a CMOS metal layer or another silicon-germanium layer, through an opening in a dielectric layer stack separating both layers. An interlayer is formed in this opening, thereby covering at least the sidewalls of the opening on the exposed surface of the another layer at the bottom of this opening. This interlayer may comprise a TiN layer in contact with the silicon-germanium layer. This interlayer can further comprise a Ti layer in between the TiN layer and the layer to be contacted. In another embodiment this interlayer comprises a TaN layer in contact with the silicon-germanium layer. This interlayer can then further comprise a Ta layer in between the TaN layer and the layer to be contacted. | 12-23-2010 |
| 20100322825 | Microfluidic molecular-flow fractionator and bioreactor with integrated active/passive diffusion barrier - A microfluidic device and method is disclosed for fractionating and/or trapping selected molecules with a diffusion barrier or porous membrane. The device includes a source fluid flow channel and a target fluid flow channel. The target fluid flow channel and the source fluid flow channel meet at cross-channel area and are in fluid communication with each other. A porous membrane separates the source fluid flow channel from the target fluid flow channel in the cross-channel area. A field-force/gradient mechanism may be positioned proximate the porous membrane with or without detection/state monitoring devices. | 12-23-2010 |
| 20110073972 | VERTICAL MIRROR IN A SILICON PHOTONIC CIRCUIT - A vertical total internal reflection (TIR) mirror and fabrication thereof is made by creating a re-entrant profile using crystallographic silicon etching. Starting with an SOI wafer, a deep silicon etch is used to expose the buried oxide layer, which is then wet-etched (in HF), opening the bottom surface of the Si device layer. This bottom silicon surface is then exposed so that in a crystallographic etch, the resulting shape is a re-entrant trapezoid with facets These facets can be used in conjunction with planar silicon waveguides to reflect the light upwards based on the TIR principle. Alternately, light can be coupled into the silicon waveguides from above the wafer for such purposes as wafer level testing. | 03-31-2011 |
| 20110078835 | SEEK-SCAN PROBE (SSP) MEMORY WITH SHARP PROBE TIPS FORMED AT CMOS-COMPATIBLE TEMPERATURES - Embodiments of a process comprising forming one or more micro-electro-mechanical (MEMS) probe on a conductive metal oxide semiconductor (CMOS) wafer, wherein each MEMS probe comprises a cantilever beam with a fixed end and a free end and wherein the CMOS wafer has circuitry thereon; forming an unsharpened tip at or near the free end of each cantilever beam; depositing a silicide-forming material over the tip; annealing the wafer to sharpen the tip; and exposing the sharpened tip. Embodiments of an apparatus comprising a conductive metal oxide semiconductor (CMOS) wafer including circuitry therein; one or more micro-electro-mechanical (MEMS) probes integrally formed on the CMOS wafer, wherein each MEMS probe comprises a cantilever beam with a fixed end and a free end and a sharpened tip at or near the free end, the sharpened tip formed by a process comprising forming an unsharpened tip at or near the free end of each cantilever beam, depositing a silicide-forming material over the unsharpened tip, annealing the wafer to sharpen the unsharpened tip, and exposing the sharpened tip. | 03-31-2011 |
