Patent application number | Description | Published |
20120295431 | METHOD FOR ETCHING GATE STACK - A method for etching a metal gate stack is provided. The method includes forming a gate stack on a substrate, where the gate stack includes a metal gate. A wet etch process is performed on the gate stack. The wet etch process includes submersing the substrate with the gate stack in an aqueous solution composed of a wet etchant and an oxidizer, removing the substrate from the solution and rinsing the solution from the etched gate stack. | 11-22-2012 |
20130122670 | PROCESS TO REMOVE Ni AND Pt RESIDUES FOR NiPtSi APPLICATIONS USING CHLORINE GAS - The invention discloses a method for cleaning residues from a semiconductor substrate during a nickel platinum silicidation process. Post silicidation residues of nickel and platinum may not be removed adequately just by an aqua regia solution (comprising a mixture of nitric acid and hydrochloric acid). Therefore, embodiments of the invention provide a multi-step residue cleaning, comprising exposing the substrate to an aqua regia solution, followed by an exposure to a chlorine gas or a solution comprising dissolved chlorine gas, which may further react with remaining platinum residues, rendering it more soluble in aqueous solution and thereby dissolving it from the surface of the substrate. | 05-16-2013 |
20130122671 | PROCESS TO REMOVE Ni AND Pt RESIDUES FOR NiPtSi APPLICATIONS - The invention discloses a method for cleaning residues from a semiconductor substrate during a nickel platinum silicidation process. Embodiments of the invention provide a multi-step cleaning process, comprising exposing the substrate to a nitric acid solution after a first anneal, followed by an aqua regia solution after a second anneal. The substrate can be optionally exposed to a hydrochloric acid solution afterward to completely remove any remaining platinum residues. | 05-16-2013 |
20130203245 | METHODS FOR PFET FABRICATION USING APM SOLUTIONS - A method for fabricating an integrated circuit from a semiconductor substrate having formed thereon over a first portion of the semiconductor substrate a hard mask layer and having formed thereon over a second portion of the semiconductor substrate an oxide layer. The first portion and the second portion are electrically isolated by a shallow trench isolation feature. The method includes removing the oxide layer from over the second portion and recessing the surface region of the second portion by applying an ammonia-hydrogen peroxide-water (APM) solution to form a recessed surface region. The APM solution is provided in a concentration of ammonium to hydrogen peroxide ranging from about 1:1 to about 1:0.001 and in a concentration of ammonium to water ranging from about 1:1 to about 1:20. The method further includes epitaxially growing a silicon-germanium (SiGe) layer on the recessed surface region. | 08-08-2013 |
20130267091 | Process to remove Ni and Pt residues for NiPtSi application using Chlorine gas - The invention discloses a method for cleaning residues from a semiconductor substrate during a nickel platinum silicidation process. Post silicidation residues of nickel and platinum may not be removed adequately just by an aqua regia solution (comprising a mixture of nitric acid and hydrochloric acid). Therefore, embodiments of the invention provide a multi-step residue cleaning, comprising exposing the substrate to an aqua regia solution, followed by an exposure to a chlorine gas or a solution comprising dissolved chlorine gas, which may further react with remaining platinum residues, rendering it more soluble in aqueous solution and thereby dissolving it from the surface of the substrate. | 10-10-2013 |
20130285159 | METHOD FOR ETCHING GATE STACK - A method for etching a metal gate stack is provided. The method includes forming a gate stack on a substrate, where the gate stack includes a metal gate. A wet etch process is performed on the gate stack. The wet etch process includes submersing the substrate with the gate stack in an aqueous solution composed of a wet etchant and an oxidizer, removing the substrate from the solution and rinsing the solution from the etched gate stack. | 10-31-2013 |
20130316472 | HIGH PRODUCTIVITY COMBINATORIAL OXIDE TERRACING AND PVD/ALD METAL DEPOSITION COMBINED WITH LITHOGRAPHY FOR GATE WORK FUNCTION EXTRACTION - Metal gate high-k capacitor structures with lithography patterning are used to extract gate work function using a combinatorial workflow. Oxide terracing, together with high productivity combinatorial process flow for metal deposition can provide optimum high-k gate dielectric and metal gate solutions for high performance logic transistors. The high productivity combinatorial technique can provide an evaluation of effective work function for given high-k dielectric metal gate stacks for PMOS and NMOS transistors, which is critical in identifying and selecting the right materials. | 11-28-2013 |
20140055152 | CIRCULAR TRANSMISSION LINE METHODS COMPATIBLE WITH COMBINATORIAL PROCESSING OF SEMICONDUCTORS - Methods and structures are described for determining contact resistivities and Schottky barrier heights for conductors deposited on semiconductor wafers that can be combined with combinatorial processing, allowing thereby numerous processing conditions and materials to be tested concurrently. Methods for using multi-ring as well as single-ring CTLM structures to cancel parasitic resistance are also described, as well as structures and processes for inline monitoring of properties. | 02-27-2014 |
20140057371 | HIGH PRODUCTIVITY COMBINATORIAL WORKFLOW FOR POST GATE ETCH CLEAN DEVELOPMENT - Combinatorial workflow is provided for evaluating cleaning processes after forming a gate structure of transistor devices, to provide optimized process conditions for gate stack formation, including metal gate stack using high-k dielectrics. NMOS and PMOS transistor devices are combinatorially fabricated on multiple regions of a substrate, with each region exposed to a different cleaning chemical and process. The transistor devices are then characterized, and the data are compared to categorize the potential damages of different cleaning chemicals and processes. Optimized chemicals and processes can be obtained to satisfy desired device requirements. | 02-27-2014 |
20140179082 | Selective Etching of Hafnium Oxide Using Non-Aqueous Solutions - Provided are methods for processing semiconductor substrates having hafnium oxide structures as well as one or more of silicon nitride, silicon oxide, polysilicon, and titanium nitride structures. Selected etching solution compositions and processing conditions provide high etching selectivity of hafnium oxide relative to these other materials. As such, hafnium oxide structures may be partially or completely removed without significant damage to other exposed structures made from these other materials. In some embodiments, the etching rate hafnium oxide is two or more times greater than the etching rate of silicon oxide and/or twenty or more times greater that the etching rate of polysilicon. The etching rate of hafnium oxide may be one and half times greater than the etching rate of silicon nitride and/or five or more times greater than the etching rate of titanium nitride. | 06-26-2014 |
20140179112 | High Productivity Combinatorial Techniques for Titanium Nitride Etching - Provided are methods of High Productivity Combinatorial testing of semiconductor substrates, each including multiple site isolated regions. Each site isolated region includes a titanium nitride structure as well as a hafnium oxide structure and/or a polysilicon structure. Each site isolated region is exposed to an etching solution that includes sulfuric acid, hydrogen peroxide, and hydrogen fluoride. The composition of the etching solution and/or etching conditions are varied among the site isolated regions to study effects of this variation on the etching selectivity of titanium nitride relative to hafnium oxide and/or polysilicon and on the etching rates. The concentration of sulfuric acid and/or hydrogen peroxide in the etching solution may be less than 7% by volume each, while the concentration of hydrogen fluoride may be between 50 ppm and 200 ppm. In some embodiments, the temperature of the etching solution is maintained at between about 40° C. and 60° C. | 06-26-2014 |