| Patent application number | Description | Published |
|---|
| 20080254630 | DEVICE AND METHODOLOGY FOR REDUCING EFFECTIVE DIELECTRIC CONSTANT IN SEMICONDUCTOR DEVICES - Method of manufacturing a semiconductor device structure, including the steps of providing a structure having an insulator layer with at least one interconnect, forming a sub lithographic template mask over the insulator layer, and selectively etching the insulator layer through the sub lithographic template mask to form sub lithographic features spanning to a sidewall of the at least one interconnect. | 10-16-2008 |
| 20080265409 | INTEGRATED CIRCUIT HARD MASK PROCESSING SYSTEM - An integrated circuit hard mask processing system is provided including providing a substrate having an integrated circuit; forming an interconnect layer over the integrated circuit; applying a low-K dielectric layer over the interconnect layer; applying a hard mask layer over the low-K dielectric layer; forming a via opening through the hard mask layer and the low-K dielectric layer to the interconnect layer; applying a first fluid and a second fluid in the via opening for removing an overhang of the hard mask layer; depositing an interconnect metal in the via opening; and chemical-mechanical polishing the interconnect metal and the ultra low-K dielectric layer. | 10-30-2008 |
| 20090008361 | OXIDANT AND PASSIVANT COMPOSITION AND METHOD FOR USE IN TREATING A MICROELECTRONIC STRUCTURE - A composition that may be used for cleaning a metal containing conductor layer, such as a copper containing conductor layer, within a microelectronic structure includes an aqueous acid, along with an oxidant material and a passivant material contained within the aqueous acid. The composition does not include an abrasive material. The composition is particularly useful for cleaning a residue from a copper containing conductor layer and an adjoining dielectric layer that provides an aperture for accessing the copper containing conductor layer within a microelectronic structure. | 01-08-2009 |
| 20090108442 | SELF-ASSEMBLED STRESS RELIEF INTERFACE - A method of forming an interconnect assembly is provided in which contacts exposed at a face of a first element such as, for example, a microelectronic element are aligned and joined with corresponding contacts of an interconnect element confronting the face of the first element. At least one of the i) the contacts of the first element, ii) the corresponding contacts of the interconnect element, iii) a joining metal between the contacts and the corresponding contacts includes a catalyst metal. Subsequently, a material including an organic component contacting the catalyst metal reacts to form volume expansion accommodation elements in the presence of the catalyst metal, the reaction being limited by proximity with the catalyst metal, such that the interconnect assembly includes volume expansion accommodation elements adjacent to the joined contacts. | 04-30-2009 |
| 20090140432 | PAD STRUCTURE TO PROVIDE IMPROVED STRESS RELIEF - A semiconductor interconnection comprises a semiconductor device, a substrate adjacent the semiconductor device, and a plurality of spring contacts on the semiconductor device or the substrate. A plurality of solder connections are on the opposite semiconductor device or substrate. Each spring contact comprises a contact surface and a conductive material on the contact surface. Upon assembly of the semiconductor device and the substrate, the conductive material on the plurality of spring contacts makes contact with each of the plurality of solder connections. The conductive material is in a liquid state at manufacturing or operating temperatures of the semiconductor device. Thus, the conductive material could be a solid at room temperature and transition to a liquid state at the semiconductor's manufacturing or operating temperatures. | 06-04-2009 |
| 20100013104 | INTEGRATED CIRCUIT HARD MASK PROCESSING SYSTEM - An integrated circuit processing system is provided including a substrate having an integrated circuit; an interconnect layer over the integrated circuit; a low-K dielectric layer over the interconnect layer; a hard mask layer over the low-K dielectric layer; a via opening through the hard mask layer and the low-K dielectric layer to the interconnect layer; and an interconnect metal in the via opening. | 01-21-2010 |
| 20100301475 | Forming Semiconductor Chip Connections - Systems and methods are disclosed that enable forming semiconductor chip connections. In one embodiment, the semiconductor chip includes a body having a polyhedron shape with a pair of opposing sides; and a solder member extending along a side that extends between the pair of opposing sides of the polyhedron shape. | 12-02-2010 |
| 20110111590 | DEVICE AND METHODOLOGY FOR REDUCING EFFECTIVE DIELECTRIC CONSTANT IN SEMICONDUCTOR DEVICES - Method of manufacturing a structure which includes the steps of providing a structure having an insulator layer with at least one interconnect, forming a sub lithographic template mask over the insulator layer, and selectively etching the insulator layer through the sub lithographic template mask to form sub lithographic features spanning to a sidewall of the plurality of interconnects. | 05-12-2011 |
