| Patent application number | Description | Published |
|---|
| 20080266984 | Programmable Heavy-Ion Sensing Device for Accelerated DRAM Soft Error Detection - Aspects of the invention relate to a programmable heavy-ion sensing device for accelerated DRAM soft error detection. Design of a DRAM-based alpha particle sensing apparatus is preferred to be used as an accelerated on-chip SER test vehicle. The sensing apparatus is provided with programmable sensing margin, refresh rate, and supply voltage to achieve various degree of SER sensitivity. In addition, a dual-mode DRAM array is proposed so that at least a portion of the array can be used to monitor high-energy particle activities during soft-error detection (SED) mode. | 10-30-2008 |
| 20080273393 | Programmable Heavy-Ion Sensing Device for Accelerated Dram Soft Error Detection - Aspects of the invention relate to a programmable heavy-ion sensing device for accelerated DRAM soft error detection. Design of a DRAM-based alpha particle sensing apparatus is preferred to be used as an accelerated on-chip SER test vehicle. The sensing apparatus is provided with programmable sensing margin, refresh rate, and supply voltage to achieve various degree of SER sensitivity. In addition, a dual-mode DRAM array is proposed so that at least a portion of the array can be used to monitor high-energy particle activities during soft-error detection (SED) mode. | 11-06-2008 |
| 20090002015 | ERROR CORRECTING LOGIC SYSTEM - The invention includes an error correcting logic system that allows critical circuits to be hardened with only one redundant unit and without loss of circuit performance. The system provides an interconnecting gate that suppresses a fault in one of at least two redundant dynamic logic gates that feed to the interconnecting gate. The system is applicable to dynamic or static logic systems. The system prevents propagation of a fault, and addresses not only soft errors, but noise-induced errors. Also, there is provided a design structure embodied in a machine readable medium used in a design process, and which includes such error correcting logic system. | 01-01-2009 |
| 20090021289 | Voltage Detection Circuit in an Integrated Circuit and Method of Generating a Trigger Flag Signal - An integrated circuit that includes at least one tunneling device voltage detection circuit for generating a trigger flag signal. The tunneling device voltage detection circuit includes first and second voltage dividers receiving a supply voltage and having corresponding respective first and second internal node output voltages. The first and second voltage dividers are configured so the first output voltage is linear relative to the supply voltage and so that the second output voltage is nonlinear relative to the supply voltage. As the supply voltage ramps up, the profiles of the first and second output voltage cross at a particular voltage. An operational amplifier circuit senses when the first and second output voltages become equal and, in response thereto, outputs a trigger signal that indicates that the supply voltage has reached a certain level. | 01-22-2009 |
| 20090033408 | Voltage Pump Circuit with an Oxide Stress Control Mechanism for use in High-Voltage Applications in an Integrated Circuit - A voltage pump circuit that has an oxide stress control mechanism is disclosed. In particular, the oxide stress control mechanism of the voltage pump circuit ensures a safe transistor gate-to-source voltage in high-voltage applications in an integrated circuit. In particular, the down level of the gate voltage of the output transistor may be conditionally limited. For example, an offset in the down level of the gate voltage is created by conditionally developing an offset voltage in the lower rail voltage of the gate driver. The offset voltage is created by directing a predetermined current through a resistance. The current is conditional such that the current is about zero when the power supply voltage is less than or equal to a predetermined level, and the current is greater than zero when the power supply voltage is greater than a predetermined level. | 02-05-2009 |
| 20090057804 | THRESHOLD VOLTAGE COMPENSATION FOR PIXEL DESIGN OF CMOS IMAGE SENSORS - The present disclosure is directed to a CMOS active pixel sensor that compensates for variations in a threshold voltage of a source follower contained therein. A structure in accordance with an embodiment includes: a replica source follower transistor; a system for creating a current in said replica source follower transistor such that a gate-source voltage of said replica source follower is substantially equal to a threshold voltage of said replica source follower; and a current mirror for biasing the isolation source follower transistor at a same current density as the replica source follower transistor. | 03-05-2009 |
| 20090141538 | Voltage Controlled Static Random Access Memory - A static random access memory (SRAM) comprising a plurality of SRAM cells, a plurality of wordlines (WL | 06-04-2009 |
| 20090144689 | Structure for a Voltage Detection Circuit in an Integrated Circuit and Method of Generating a Trigger Flag Signal - A design structure for an integrated circuit that includes at least one tunneling device voltage detection circuit for generating a trigger flag signal. The tunneling device voltage detection circuit includes first and second voltage dividers receiving a supply voltage and having corresponding respective first and second internal node output voltages. The first and second voltage dividers are configured so the first output voltage is linear relative to the supply voltage and so that the second output voltage is nonlinear relative to the supply voltage. As the supply voltage ramps up, the profiles of the first and second output voltage cross at a particular voltage. An operational amplifier circuit senses when the first and second output voltages become equal and, in response thereto, outputs a trigger signal that indicates that the supply voltage has reached a certain level. | 06-04-2009 |
| 20090153172 | STRUCTURE FOR INDICATING STATUS OF AN ON-CHIP POWER SUPPLY SYSTEM - A design structure embodied in a machine readable medium used in a design process includes a system for indicating status of an on-chip power supply system with multiple power supplies, having a power system status register for receiving digital compliance signals, each compliance signal associated with one of the multiple power supplies, and having an associated compliance level, wherein each digital compliance signal indicates whether its associated power supply is operating at the associated compliance level, and wherein the power system status register generates a power supply status signal based on the digital compliance signals indicating status of the digital compliance signals; and an output for outputting the power supply status signal, wherein if a power supply is operating at its associated compliance level, the power supply status signal indicates that the power supply is passing, otherwise the power supply status signal indicates that the power supply is failing. | 06-18-2009 |
| 20090158092 | SYSTEM AND METHOD FOR INDICATING STATUS OF AN ON-CHIP POWER SUPPLY SYSTEM - The status of multiple on-chip power supply systems is indicated for use in modifying chip test flow and diagnosing chip failure. Digital compliance signals are received, each compliance signal associated with one of multiple on-chip power supplies. Each power supply has an associated compliance level, and each compliance signal indicates whether its associated power supply is operating at the associated compliance level. The compliance signals are converted into a power supply status signal indicating status of the compliance signals associated with the power supply. The power supply status signal is output. If a power supply is operating at its associated compliance level, the output power supply status signal indicates that the power supply is passing. If the power supply is not operating at its associated compliance level, the output power supply status signal indicates that the power supply is failing. If a power supply is failing, a memory test may be aborted, simplifying chip failure diagnosis. | 06-18-2009 |
| 20090206915 | Two Stage Voltage Boost Circuit, IC and Design Structure - A two stage voltage boost circuit, IC and design structure are disclosed for boosting a supply voltage using gate control circuitry to reduce gate oxide stress, thus allowing lower voltage level FETs to be used. The voltage boost circuit may include a first stage for boosting the supply voltage to a first boosted voltage; a first passgate coupled to the first stage; a first gate control circuit for generating an on-state gate voltage level for the first passgate adjusted to reduce gate oxide voltage stress on the passgate; a second stage for boosting the first boosted voltage to a second boosted voltage; a second passgate coupled to the second stage, and a gate control circuit for generating an on-state gate voltage level for the second passgate adjusted to reduce gate oxide voltage stress on the second pass-gate. | 08-20-2009 |
| 20090206916 | Voltage Boost System, IC and Design Structure - A voltage boost system, IC and design structure are disclosed for boosting a supply voltage while preventing forward biasing of n-well structures. The voltage boost system may include a first voltage boost circuit producing a first boosted voltage using at least one voltage boost sub-circuit, each of the at least one voltage boost sub-circuit having an output passgate in an n-well; a second voltage boost circuit producing a second boosted voltage, the n-well of each output passgate being biased using the second boosted voltage, wherein the second boosted voltage is greater than the first boosted voltage. Voltage boost sub-circuits may use gate control circuitry to reduce gate oxide stress, thus allowing lower voltage level FETs to be used. | 08-20-2009 |
| 20090206917 | Two Stage Voltage Boost Circuit With Precharge Circuit Preventing Leakage, IC and Design Structure - A two stage voltage boost circuit, IC and design structure are disclosed for boosting a supply voltage using gate control circuitry to reduce gate oxide stress, thus allowing lower voltage level FETs to be used. The voltage boost circuit may include a first stage for boosting the supply voltage to a first boosted voltage and a second stage for boosting the first boosted voltage to a second boosted voltage. Each stage may include a passgate and a gate control circuit for generating an on-state gate voltage level for the respective passgate adjusted to reduce gate oxide voltage stress on the passgate. The circuit may also include a precharge circuit for coupling a voltage on a high node of the second stage to a gate node of a precharge transistor thereof for disabling the precharge transistor and preventing leakage back to a power supply voltage. | 08-20-2009 |
| 20090243733 | DESIGN STRUCTURE FOR TRANSFORMING AN INPUT VOLTAGE TO OBTAIN LINEARITY BETWEEN INPUT AND OUTPUT FUNCTIONS AND SYSTEM AND METHOD THEREOF - A design structure is embodied in a machine readable medium for designing, manufacturing, or testing a design. The design structure includes a first structure for determining a non-linear characteristic of the input voltage to the output frequency response, the first design structure providing a tunneling-based current relationship with the input voltage. Also disclosed is a system and a method of implementing such structure. | 10-01-2009 |
| 20090261890 | REGULATED VOLTAGE BOOST CHARGE PUMP FOR AN INTEGRATED CIRCUIT DEVICE - An apparatus and method for a regulated voltage boost charge pump for an integrated circuit (IC) device. The charge pump generally includes a plurality of switching networks and a lift capacitor that are intermittently coupled to an output capacitor or to a regulating transistor, a differential error amplifier biasing a gate terminal of the transistor, and a controller configured to alternate states of switches in the switching networks in a pre-selected timing relationship with a clock signal of the IC device. | 10-22-2009 |
| 20100001788 | SYSTEM TO EVALUATE CHARGE PUMP OUTPUTS AND ASSOCIATED METHODS - A system to evaluate charge pump output may include a comparator to compare a charge pump output voltage to a reference voltage to generate a comparison result. The system may also include a divider to divide down a clock signal. The system may further include a logical conjunction unit to operate on the comparison result and the divided down clock signal. | 01-07-2010 |
| 20100014373 | REGULATING ELECTRICAL FUSE PROGRAMMING CURRENT - An apparatus for regulating eFUSE programming current includes a current control generator receiving an input reference current through a first current path of reference fuses, the input reference current proportional to a desired eFUSE programming current; a second current path including a reference programming FET and a second group of reference fuses; and a voltage comparator coupled to a gate terminal of the reference programming FET so as to adjust the gate voltage of the reference programming FET to equalize a first voltage across the first current path with a second voltage across the second current path. The gate voltage of the reference programming FET is an output of the current control generator, coupled to corresponding gates of one or more selected programming devices of an eFUSE array such that the selected programming devices source the desired eFUSE programming current to a selected eFUSE to be programmed. | 01-21-2010 |
| 20110032025 | PROGRAMMABLE SEMICONDUCTOR DEVICE - A programmable device includes a substrate ( | 02-10-2011 |
| 20110088008 | METHOD FOR CONVERSION OF COMMERCIAL MICROPROCESSOR TO RADIATION-HARDENED PROCESSOR AND RESULTING PROCESSOR - A method is provided to convert commercial microprocessors to radiation-hardened processors and, more particularly, a method is provided to modify a commercial microprocessor for radiation hardened applications with minimal changes to the technology, design, device, and process base so as to facilitate a rapid transition for such radiation hardened applications. The method is implemented in a computing infrastructure and includes evaluating a probability that one or more components of an existing commercial design will be affected by a single event upset (SEU). The method further includes replacing the one or more components with a component immune to the SEU to create a final device. | 04-14-2011 |
