| Patent application number | Description | Published |
|---|
| 20080272831 | Charge Pump CMOS Circuit - A charge pump CMOS circuit comprises a differential input stage with two parallel circuit branches. Each of the parallel circuit branches has a diode-connected MOS transistor connected in series with a complementary input MOS transistor. There is a common tail current source for both circuit branches. The diode-connected MOS transistors each have their gate/drain node connected to corresponding current sources. The charge pump CMOS circuit is suitable for use in an oscillator. | 11-06-2008 |
| 20080272833 | Charge Pump - A charge pump for generating an input voltage for an operational amplifier includes a storage capacitor for storing a charge pump voltage and a flying capacitor configured to be charged during a first phase of operation and discharged during a second phase of operation. Discharging the flying capacitor charges the storage capacitor. A current source supplies the flying capacitor and a switching means switches current from the current source through the flying capacitor in a first direction during the first phase and in a second opposite direction during the second phase. | 11-06-2008 |
| 20090039845 | METHOD AND APPARATUS FOR POWER MANAGEMENT OF A LOW DROPOUT REGULATOR - A method of switching a low dropout regulator includes determining an actual active time of a power request from an electronic device; enabling the low dropout regulator in response to said power request at a time corresponding to a start of the actual active time of the power request for an active enabled time having a duration at least the same as the actual active time and long enough to sufficiently settle the output voltage of the low dropout regulator; and disabling the low dropout regulator. In embodiments, the active enabled time is prolonged beyond the actual active time of the power request for all or at least some power requests. An electronic device includes circuits for controlling the switching of a low dropout in the described manner. | 02-12-2009 |
| 20090039945 | Bias Current Generator - An electronic device generates a current with a predetermined temperature coefficient. The circuit comprises a temperature coefficient (TC) component receiving a bias current, a differential amplifier providing a buffered output voltage based on the voltage across the TC component and a resistor receiving an TC current based on the differential amplifier output voltage. The differential amplifier has a predetermined input related offset which decreases the voltage drop across the resistor. The temperature coefficient component could have either a negative temperature component (NTC) or a positive temperature component (PTC). | 02-12-2009 |
| 20090051331 | Method and Circuit for Controlling the Refresh Rate of Sampled Reference Voltages - The present invention relates to controlling the refresh rate of the reference voltage on a sampling capacitor (C | 02-26-2009 |
| 20090058493 | Signal Level Converter - An electronic device with a supply voltage level converter converts a signal from a first low supply voltage level to a second high supply voltage level includes; a first pair of cross coupled MOS transistors compliant with the second supply voltage level, each having a source coupled to the second supply voltage level and providing complementary output signals at respective drains; driven by a second pair of common gate MOS transistors compliant with the second supply voltage; driven by a third pair of common gate MOS transistors compliant with the first voltage level; and driven by first and second inverters coupled in a chain and supplied by the first supply voltage level, each having an output connected to the source of a transistor in a third pair. | 03-05-2009 |
| 20090066556 | Method and Device for Controlling a Successive Approximation Register Analog to Digital Converter - A method for controlling a successive approximation register analog to digital converter comprising connecting a first side of a capacitor to a first comparator input, during a sampling phase connecting the first side of a capacitor to an input and connecting a second side of the capacitor to a mid-voltage, following the sampling phase disconnecting the first side of the capacitor from the input and disconnecting the second side of the capacitor from the mid-voltage and autozeroing the comparator. | 03-12-2009 |
| 20090096433 | LDO With Large Dynamic Range of Load Current and Low Power Consumption - An electronic device has an LDO regulator for varying loads. The LDO regulator includes a primary supply node coupled to a primary voltage supply. An output node provides a secondary supply voltage and a load current. A bias current source generates a bias current. A gain stage coupled to the bias current source increases the maximum available load current. The gain stage includes a first MOS transistor biased in weak inversion coupled to a current mirror which mirrors the drain current through the first MOS transistor to the output node. The gate-source voltage of the first MOS transistor increases in response to a decreasing secondary supply voltage level at the output node to increase the available load current. | 04-16-2009 |
| 20090121754 | Power-On Reset Circuit - An integrated circuit provides a power on reset signal with respect to a supply voltage level supplying the electronic device. The integrated circuit comprises a bias current generating stage having a first current mirror and an output stage having first, second and third series connected MOS transistors. A connection between the second MOS transistor and the third MOS transistor forms a POR output node. A gate of the second MOS transistor and a gate of the third MOS transistor are coupled to each other and to the first current mirror. This allows a current through the third MOS transistor when the supply voltage is higher than a first MOS transistor threshold and a current through the second MOS transistor only when the supply voltage is greater than or equal to the sum of the first MOS transistor threshold and a second MOS transistor threshold voltage. | 05-14-2009 |
