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Joffe, US
Alexander Joffe, Palo Alto, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20080320485 | Logic for Synchronizing Multiple Tasks at Multiple Locations in an Instruction Stream - Logic (also called “synchronizing logic”) in a co-processor (that provides an interface to memory) receives a signal (called a “declaration”) from each of a number of tasks, based on an initial determination of one or more paths (also called “code paths”) in an instruction stream (e.g. originating from a high-level software program or from low-level microcode) that a task is likely to follow. Once a task (also called “disabled” task) declares its lack of a future need to access a shared data, the synchronizing logic allows that shared data to be accessed by other tasks (also called “needy” tasks) that have indicated their need to access the same. Moreover, the synchronizing logic also allows the shared data to be accessed by the other needy tasks on completion of access of the shared data by a current task (assuming the current task was also a needy task). | 12-25-2008 |
| 20090282408 | SYSTEMS AND METHODS FOR MULTI-TASKING, RESOURCE SHARING, AND EXECUTION OF COMPUTER INSTRUCTIONS - In a multi-tasking pipelined processor, consecutive instructions are executed by different tasks, eliminating the need to purge an instruction execution pipeline of subsequent instructions when a previous instruction cannot be completed. The tasks do not share registers which store task-specific values, thus eliminating the need to save or load registers when a new task is scheduled for execution. If an instruction accesses an unavailable resource, the instruction becomes suspended, allowing other tasks' instructions to be executed instead until the resource becomes available. Task scheduling is performed by hardware; no operating system is needed. Simple techniques are provided to synchronize shared resource access between different tasks. | 11-12-2009 |
Daniel M. Joffe, Owens Crossroads, AL US
| Patent application number | Description | Published |
|---|---|---|
| 20090296302 | SURGE PROTECTION SYSTEMS AND METHODS FOR OUTSIDE PLANT ETHERNET - The present disclosure generally pertains to surge protection systems that protect outside plant equipment from high-energy surges. In one exemplary embodiment, a protection system is used for protecting Ethernet equipment that is coupled to an outside Ethernet cable. The protection system provides protection and remains capable of coupling signal energy between an Ethernet cable and Ethernet equipment without significantly degrading Ethernet performance. However, the protection system, while allowing the desirable Ethernet signals to pass between the cable and the equipment, prevents the electrical voltages and currents of high-energy surges, such as surges from lightning or AC power faults, from damaging the Ethernet equipment. | 12-03-2009 |
| 20100322363 | ADAPTIVE INTERFERENCE CANCELING SYSTEM AND MEHOD - A communication system adaptively cancels noise and/or interference from signals communicated through a communication channel, such as signals communicated by a telecommunication network. The system, based on a common mode signal of a received signal, generates an estimate of noise or interference within a differential mode signal of the received signal. The system then subtracts the estimate from the differential mode signal in an effort to remove noise from the differential mode signal thereby providing a differential mode signal that is substantially free of the estimated noise or interference. | 12-23-2010 |
| 20110128661 | SURGE PROTECTION SYSTEMS AND METHODS FOR ETHERNET COMMUNICATION EQUIPMENT IN OUTSIDE PLANT ENVIRONMENTS - The present disclosure generally pertains to surge protection systems that protect outside plant equipment from high-energy surges. In one exemplary embodiment, a protection system is used for protecting Ethernet equipment that is coupled to an outside Ethernet cable. The protection system provides protection and remains capable of coupling signal energy between an Ethernet cable and Ethernet equipment without significantly degrading Ethernet performance. However, the protection system, while allowing the desirable Ethernet signals to pass between the cable and the equipment, prevents the electrical voltages and currents of high-energy surges, such as surges from lightning or AC power faults, from damaging the Ethernet equipment. | 06-02-2011 |
David Joffe, Boulder, CO US
| Patent application number | Description | Published |
|---|---|---|
| 20110015503 | MEDICAL APPARATUS FOR COLLECTING PATIENT ELECTROENCEPHALOGRAM (EEG) DATA - The EEG Processing Unit comprises a semi-rigid framework which substantially conforms to the Patient's head and supports a set of electrodes in predetermined loci on the Patient's head to ensure proper electrode placement. The EEG Processing Unit includes automated connectivity determination apparatus which can use pressure-sensitive electrode placement ensuring proper contact with Patient's scalp and also automatically verifies electrode placement via measurements of electrode impedance through automated impedance checking. Voltages generated by the electrodes are amplified and filtered before being transmitted to an analysis platform, which can be a Physician's laptop computer system, either wirelessly or via a set of tethering wires. The EEG Processing Unit includes an automatic artifacting capability which identifies when there is sufficient clean data compiled in the testing session. This process automatically eliminates muscle- or other physical-artifact-related voltages. Clean data, which represents real brain voltages as opposed to muscle- or physical-artifact-related voltages, thereby are produced. | 01-20-2011 |
Michael A. Joffe, Harvard, MA US
| Patent application number | Description | Published |
|---|---|---|
| 20080205078 | ILLUMINATION TILES AND RELATED METHODS - Illumination assemblies, components, and related methods are described. A plurality of illumination tiles may be arranged in a two-dimensional array. In one embodiment, an illumination tile comprises at least one solid state light-emitting device and a light guide including an edge constructed and arranged to receive light from the solid state light-emitting device, and a top emission surface constructed and arranged to emit light received by the edge, wherein the solid state light-emitting device is disposed under the top emission surface. In another embodiment, an illumination tile comprises at least one solid state light-emitting device and a light guide including a light input portion including an edge constructed and arranged to receive light from the light-emitting device and a top surface, and a light extraction portion including a top emission surface constructed and arranged to emit light received by the edge, wherein the top surface of the light input portion is offset vertically from the top emission surface of the light extraction portion. | 08-28-2008 |
| 20080205080 | TILED ILLUMINATION ASSEMBLY AND RELATED METHODS - Illumination assemblies, components, and related methods are described. An illumination assembly is provided that comprises a plurality of illumination tiles each having a light emission surface. The plurality of illumination tiles are arranged in a two-dimensional array. The illumination tiles are constructed and arranged so as to provide a substantially contiguous illumination surface comprising the light emission surfaces of the plurality of the illumination tiles. Each illumination tile is illuminated by at least one solid state light-emitting device. A method of local dimming an illumination assembly of a display (e.g., LCD) backlight unit is also provided. | 08-28-2008 |
| 20110121703 | THERMAL MANAGEMENT SYSTEMS FOR LIGHT EMITTING DEVICES AND SYSTEMS - One or more embodiments presented herein include a light emitting system and/or device that can include a thermal management system. The thermal management system can provide for transport and/or dissipation of heat generated by a light emitting device. | 05-26-2011 |
Neil Joffe, Mountain View, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20090100288 | FAST SOFTWARE FAULT DETECTION AND NOTIFICATION TO A BACKUP UNIT - A method and system for quickly informing a backup unit that a primary unit has failed. Normally an exception handler is activated when a software failure occurs and network controller chips or the ASIC interface to a signal bus can operate even though there is a software failure. A software failure notification packet is programmed and stored in a location that is not affected by a software system failure. When a software failure occurs, control is shifted to the exception handler. The exception handler sends a pre-established and pre-addressed packet to the network controller card which transmits this packet to the backup unit. Upon receipt of the packet, the backup unit goes into operation. In some alternate embodiments that include multiple line cards in a single unit, the exception handler sends a signal to a backup unit via a signal bus or a data bus. | 04-16-2009 |
Nitay Joffe, Palo Alto, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20090070308 | Checkpointing Iterators During Search - Tools and techniques are described herein for checkpointing iterators during search. These tools may provide methods that include instantiating iterators in response to a search request. The iterators include fixed state information that remains constant over a life of the iterator, and further include dynamic state information that is updated over the life of the iterator. The iterators traverse through postings lists in connection with performing the search request. As the iterators traverse the posting lists, the iterators may update their dynamic state information. The iterators may then evaluate whether to create checkpoints, with the checkpoints including representations of the dynamic state information. | 03-12-2009 |
Rodney Lance Joffe, Tempe, AZ US
| Patent application number | Description | Published |
|---|---|---|
| 20100077462 | SECURE DOMAIN NAME SYSTEM - A method and system for authenticating answers to Domain Name System (DNS) queries originating from recursive DNS servers are provided. A verification component provides a verification that a DNS query originated from the recursive DNS server. An authoritative DNS server receives the query via a network, such as the Internet, and provides an answer to the query to an authentication component. The authentication component then provides an authentication, such as a digital signature, which confirms that the received answer was provided by the authoritative DNS server, and then communicates the answer and the authentication to the verification component via the network. The verification component then verifies that the authentication corresponds to the received answer and sends the answer to the recursive DNS server. When the verification component receives an answer in the absence of a corresponding authentication, the verification component drops the answer. | 03-25-2010 |
Scott M. Joffe, Austin, TX US
| Patent application number | Description | Published |
|---|---|---|
| 20100037496 | Announcement device - The present invention relates to an announcement device that incorporates a set of indicia that has been manufactured using an electrodeposition/electroforming process. The set of indicia can include pictorial graphics, text, images, communicating marks, or illustrative marks that communicate information related to an event such as a wedding, a social event, a religious event, a business event, or a family event. | 02-18-2010 |
| 20100050484 | Insignia device - The present invention relates to an insignia device that incorporates a set of indicia that has been manufactured using an electrodeposition/electroforming process. The set of indicia can include business letterheads, personal letterheads, logos, pictorial graphics, text, images, communicating marks, or illustrative marks where the set of indicia has been mounted on a mounting service. | 03-04-2010 |