Patent application number | Description | Published |
20080208510 | Parameterized Signal Conditioning - A coupling unit is adapted to be coupled between a first and a second unit to be tested. Said coupling unit comprises a first signal path that is adapted to provide a signal connection between at least one terminal of the first unit to be tested and at least one terminal of the second unit to be tested. The first signal path comprises a signal conditioning facility adapted for receiving a first signal from the first unit to be tested, for conditioning said first signal in accordance with predefined parameters, and for providing the conditioned first signal to the second unit to be tested. | 08-28-2008 |
20090063100 | Analog signal test using a-priori information - The present invention relates to a method and a corresponding system ( | 03-05-2009 |
20090219010 | CALIBRATING SIGNALS BY TIME ADJUSTMENT - A signal processing device having an adjustment unit for adjusting a time duration of each of a plurality of signals individually in accordance with an amplitude of the respective signal to thereby generate calibrated signals, and a combining unit for combining the calibrated signals. | 09-03-2009 |
20090322574 | TIME-TO-DIGITAL CONVERSION WITH DELAY CONTRIBUTION DETERMINATION OF DELAY ELEMENTS - A time-to-digital converter includes at least one chain of delay elements, a status of which represents a digital signal relating to a time interval to be converted. The converter includes a provider for providing trigger signals having statistically equally distributed variable positions relative to a pulse forwarded in the chain of delay elements, a capturer for capturing the status of the chain of delay elements in response to the calibration trigger signals, the status depending on delay times of the delay elements, a determiner for determining an actual contribution of at least some of the delay elements to an overall delay of the chain of delay elements on the basis of occurrences of pulse positions in response to the calibration trigger signals. The converter is configured to take into account the actual contribution of at least some of the delay elements when converting the time interval into said digital signal. | 12-31-2009 |
20100011252 | FORMAT TRANSFORMATION OF TEST DATA - A device for processing test data, the device having a data input interface adapted for receiving primary test data indicative of a test carried out for testing a device under test, the primary test data being provided in a primary format, a processing unit adapted for generating secondary test data in a secondary format by transforming, by carrying out a coordinate transformation, the primary test data from the primary format into the secondary format, and a data output interface adapted for providing the secondary test data in the secondary format for storing the secondary test data in a plurality of storage units. | 01-14-2010 |
20100045499 | ASYNCHRONOUS SIGMA-DELTA DIGITAL-ANALOG CONVERTER - An asynchronous sigma delta digital to analog converter for converting a digital input signal into an analog output signal, the digital to analog converter having an asynchronous sigma delta modulator having a low pass filter and a comparator and being supplied with the digital input signal, and a clock sample unit adapted to sample a signal processed by the comparator based on a clock signal, thereby generating the analog output signal. | 02-25-2010 |
20110032829 | METHOD AND APPARATUS FOR DETERMINING RELEVANCE VALUES FOR A DETECTION OF A FAULT ON A CHIP AND FOR DETERMINING A FAULT PROBABILITY OF A LOCATION ON A CHIP - A method for determining relevance values representing a relevance of a combination of an input node of a first number of input nodes with a measurement node of a second number of measurement nodes for a detection of a fault on a chip applies a third number of tests at the first number of input nodes, measures for each test of the third plurality of tests a signal at each of the second number of measurement nodes to obtain for each measurement node of the second number of measurement nodes a third number of measurement values, and determines the relevance values, wherein each relevance value is calculated based on a correlation between the third number of test input choices defined for the input node of the respective combination and the third number of measurement values associated to the measurement node of the respective combination. | 02-10-2011 |
20110041012 | METHOD OF SHARING A TEST RESOURCE AT A PLURALITY OF TEST SITES, AUTOMATED TEST EQUIPMENT, HANDLER FOR LOADING AND UNLOADING DEVICES TO BE TESTED AND TEST SYSTEM - A method of sharing a test resource at a plurality of test sites executes respective test flows at the plurality of test sites with an offset in time, the respective test flows accessing the test resource at a predetermined position in the test flow. | 02-17-2011 |
20110140737 | APPARATUS AND METHOD FOR ESTIMATING DATA RELATING TO A TIME DIFFERENCE AND APPARATUS AND METHOD FOR CALIBRATING A DELAY LINE - An apparatus for estimating data relating to a time difference between two events includes a delay line having a plurality of stages. Each stage has a delay difference between a first delay in a first part and a second delay in a second part. This delay difference is measured by a phase arbiter in each stage, which outputs an indication signal indicating whether the first event of two events in the first part precedes or succeeds a second event of the two events in the second part. A summation device is provided for summing over the indication signals of the plurality of stages to obtain a sum value. The sum value indicates a time difference estimate. | 06-16-2011 |
20110197086 | DATA PROCESSING UNIT AND A METHOD OF PROCESSING DATA - A data processing unit has a time information provider for processing a clock or a strobe signal, configured to provide a digitized clock or strobe time information on the basis of the clock or strobe signal and at least one data extraction unit, coupled to the time information provider and configured to select data from a sequence of data samples of a data signal depending on the digitized clock or strobe time information. | 08-11-2011 |
20110231464 | STATE MACHINE AND GENERATOR FOR GENERATING A DESCRIPTION OF A STATE MACHINE FEEDBACK FUNCTION - An embodiment of a state machine for generating a pseudo-random word stream, each word of the word stream including a plurality of subsequent bits of a pseudo-random bit sequence includes a plurality of clock registers and a feedback circuit coupled to the registers and adapted to provide a plurality of feedback signals to the registers based on a feedback function and a plurality of register output signals of the registers, wherein the state machine is configured such that a first word defined by the plurality of register output signals includes a first set of subsequent bits of a pseudo-random bit stream and such that a subsequent second word defined by the plurality of register output signals includes a second set of subsequent bits of a pseudo-random bit stream. | 09-22-2011 |
20110254719 | DECORRELATION OF DATA BY USING THIS DATA - A device for processing data adapted for being converted between an analog format and a digital format, the device having a scrambling unit adapted for scrambling the data based on at least a part of the data to thereby decorrelate the data in the analog format with respect to the data in the digital format. | 10-20-2011 |
20110276302 | RE-CONFIGURABLE TEST CIRCUIT, METHOD FOR OPERATING AN AUTOMATED TEST EQUIPMENT, APPARATUS, METHOD AND COMPUTER PROGRAM FOR SETTING UP AN AUTOMATED TEST EQUIPMENT - A re-configurable test circuit for use in an automated test equipment includes a test circuit, a test processor and a programmable logic device. The pin electronics circuit is configured to interface the re-configurable test circuit with a DUT. The test processor includes a timing circuit configured to provide one or more adjustable-timing signals having adjustable timing. The programmable logic device is configured to implement a state machine, a state sequence of which depends on one or more input signals received from the pin electronics circuit, to provide an output signal, which depends on a current or previous state of the state machine, to the pin electronics circuit in response to the signal(s) received from the pin electronics circuit. The test processor is coupled to the programmable logic device to provide at least one of the adjustable-timing signal(s) to the programmable logic device to define timing of the programmable logic device. | 11-10-2011 |
20120232826 | APPARATUS AND METHOD FOR WIRELESS TESTING OF A PLURALITY OF TRANSMIT PATHS AND A PLURALITY OF RECEIVE PATHS OF AN ELECTRONIC DEVICE - An apparatus for wireless testing, the apparatus comprising: a test interface, a test generator, a test module, and an analysis module. The test interface is coupled to an electronic device and is configured to transmit data to the electronic device and to receive data from the electronic device. The test generator drives the electronic device through the test interface to vary the beam direction. The test module determines a plurality of transmit values of a transmit parameter based on the test signal wirelessly received from the electronic device using at least one static antenna for receiving the test signal. Each transmit value of the transmit parameter is associated with a different beam direction. The analysis module provides an assessment of the plurality of transmit paths of the electronic device based on the plurality of transmit values. | 09-13-2012 |
20120256639 | APPARATUS COMPRISING A RECURSIVE DELAYER AND METHOD FOR MEASURING A PHASE NOISE - Embodiments of the invention provide an apparatus for measuring a phase noise of a test signal. The apparatus comprises a recursive delayer, a combiner and a phase noise determinator. The recursive delayer is configured to provide a delayed signal on the basis of the test signal. The combiner is configured to combine a first signal with a second signal to provide a combiner output signal. The first signal is based on the test signal or a signal identical to the test signal. The second signal is based on the delayed signal or a signal identical to the delayed signal. The phase noise determinator is configured to provide a phase noise information that depends on the combiner output signal. | 10-11-2012 |
20130198252 | APPARATUS FOR DETERMINING A NUMBER OF SUCCESSIVE EQUAL BITS PRECEDING AN EDGE WITHIN A BIT STREAM AND APPARATUS FOR RECONSTRUCTING A REPETITIVE BIT SEQUENCE - An apparatus for determining a number of successive equal bits preceding an edge within a bit stream including a repetitive bit sequence includes an edge number determiner, an edge selector, a time stamper and an equal bits determiner. The edge number determiner determines a preset number of edges. The preset number of edges is coprime to a number of edges of the repetitive bit sequence or coprime to a maximal number of edges of the repetitive bit sequence. The edge selector selects edges of the bit stream spaced apart from each other by the preset number of edges. Further, the time stamper determines a time stamp for each selected edge of the bit stream and the equal bits determiner determines the number of successive equal bits preceding the edge based on determined time stamps of selected edges. | 08-01-2013 |
20140336958 | Techniques for Determining a Fault Probability of a Location on a Chip - A method for determining relevance values representing a relevance of a combination of an input node of a first number of input nodes with a measurement node of a second number of measurement nodes for a detection of a fault on a chip applies a third number of tests at the first number of input nodes, measures for each test of the third plurality of tests a signal at each of the second number of measurement nodes to obtain for each measurement node of the second number of measurement nodes a third number of measurement values, and determines the relevance values, wherein each relevance value is calculated based on a correlation between the third number of test input choices defined for the input node of the respective combination and the third number of measurement values associated to the measurement node of the respective combination. | 11-13-2014 |
20150039927 | Device Under Test Data Processing Techniques - A data processing unit has a time information provider for processing a clock or a strobe signal, configured to provide a digitized clock or strobe time information on the basis of the clock or strobe signal and at least one data extraction unit, coupled to the time information provider and configured to select data from a sequence of data samples of a data signal depending on the digitized clock or strobe time information. | 02-05-2015 |