| Patent application number | Description | Published |
|---|
| 20080208510 | Parameterized Signal Conditioning - A coupling unit is adapted to be coupled between a first and a second unit to be tested. Said coupling unit comprises a first signal path that is adapted to provide a signal connection between at least one terminal of the first unit to be tested and at least one terminal of the second unit to be tested. The first signal path comprises a signal conditioning facility adapted for receiving a first signal from the first unit to be tested, for conditioning said first signal in accordance with predefined parameters, and for providing the conditioned first signal to the second unit to be tested. | 08-28-2008 |
| 20090063100 | Analog signal test using a-priori information - The present invention relates to a method and a corresponding system ( | 03-05-2009 |
| 20090219010 | CALIBRATING SIGNALS BY TIME ADJUSTMENT - A signal processing device having an adjustment unit for adjusting a time duration of each of a plurality of signals individually in accordance with an amplitude of the respective signal to thereby generate calibrated signals, and a combining unit for combining the calibrated signals. | 09-03-2009 |
| 20090322574 | TIME-TO-DIGITAL CONVERSION WITH DELAY CONTRIBUTION DETERMINATION OF DELAY ELEMENTS - A time-to-digital converter includes at least one chain of delay elements, a status of which represents a digital signal relating to a time interval to be converted. The converter includes a provider for providing trigger signals having statistically equally distributed variable positions relative to a pulse forwarded in the chain of delay elements, a capturer for capturing the status of the chain of delay elements in response to the calibration trigger signals, the status depending on delay times of the delay elements, a determiner for determining an actual contribution of at least some of the delay elements to an overall delay of the chain of delay elements on the basis of occurrences of pulse positions in response to the calibration trigger signals. The converter is configured to take into account the actual contribution of at least some of the delay elements when converting the time interval into said digital signal. | 12-31-2009 |
| 20100011252 | FORMAT TRANSFORMATION OF TEST DATA - A device for processing test data, the device having a data input interface adapted for receiving primary test data indicative of a test carried out for testing a device under test, the primary test data being provided in a primary format, a processing unit adapted for generating secondary test data in a secondary format by transforming, by carrying out a coordinate transformation, the primary test data from the primary format into the secondary format, and a data output interface adapted for providing the secondary test data in the secondary format for storing the secondary test data in a plurality of storage units. | 01-14-2010 |
| 20100045499 | ASYNCHRONOUS SIGMA-DELTA DIGITAL-ANALOG CONVERTER - An asynchronous sigma delta digital to analog converter for converting a digital input signal into an analog output signal, the digital to analog converter having an asynchronous sigma delta modulator having a low pass filter and a comparator and being supplied with the digital input signal, and a clock sample unit adapted to sample a signal processed by the comparator based on a clock signal, thereby generating the analog output signal. | 02-25-2010 |
| 20110032829 | METHOD AND APPARATUS FOR DETERMINING RELEVANCE VALUES FOR A DETECTION OF A FAULT ON A CHIP AND FOR DETERMINING A FAULT PROBABILITY OF A LOCATION ON A CHIP - A method for determining relevance values representing a relevance of a combination of an input node of a first number of input nodes with a measurement node of a second number of measurement nodes for a detection of a fault on a chip applies a third number of tests at the first number of input nodes, measures for each test of the third plurality of tests a signal at each of the second number of measurement nodes to obtain for each measurement node of the second number of measurement nodes a third number of measurement values, and determines the relevance values, wherein each relevance value is calculated based on a correlation between the third number of test input choices defined for the input node of the respective combination and the third number of measurement values associated to the measurement node of the respective combination. | 02-10-2011 |
| 20110041012 | METHOD OF SHARING A TEST RESOURCE AT A PLURALITY OF TEST SITES, AUTOMATED TEST EQUIPMENT, HANDLER FOR LOADING AND UNLOADING DEVICES TO BE TESTED AND TEST SYSTEM - A method of sharing a test resource at a plurality of test sites executes respective test flows at the plurality of test sites with an offset in time, the respective test flows accessing the test resource at a predetermined position in the test flow. | 02-17-2011 |
| 20110140737 | APPARATUS AND METHOD FOR ESTIMATING DATA RELATING TO A TIME DIFFERENCE AND APPARATUS AND METHOD FOR CALIBRATING A DELAY LINE - An apparatus for estimating data relating to a time difference between two events includes a delay line having a plurality of stages. Each stage has a delay difference between a first delay in a first part and a second delay in a second part. This delay difference is measured by a phase arbiter in each stage, which outputs an indication signal indicating whether the first event of two events in the first part precedes or succeeds a second event of the two events in the second part. A summation device is provided for summing over the indication signals of the plurality of stages to obtain a sum value. The sum value indicates a time difference estimate. | 06-16-2011 |
