| Patent application number | Description | Published |
|---|
| 20090013290 | Method and System for Electromigration Analysis on Signal Wiring - The invention relates to an electromigration analysis method and a system for analyzing one or more nets in a digital integrated circuit design that are at risk of electromigration. The method comprises the steps of providing at least one interconnect between a driver cell and at least one load cell; applying same extracted netlist data for noise and/or timing analysis and for electromigration analysis; modeling the driver cell by a train of trapezoidal voltage pulses transmitted from the driver cell to the one or more load cells through the at least one interconnect; extracting at least a slew rate of a driver voltage signal (U | 01-08-2009 |
| 20100037198 | PORT ASSIGNMENT IN HIERARCHICAL DESIGNS BY ABSTRACTING MACRO LOGIC - A method to reduce the problem complexity maintains a relatively high quality port assignment by abstracting local connections in the macro when performing the port assignment. This is done for netlength, congestion as well as timing. The internal netlist of the macro is abstracted in such a way that the optimization of the external interconnect can be done in an efficient manner. Three levels of abstractions are described. A first level optimizes the top level interconnect, a second level optimizes the top level and macro interconnects, while a third level optimizes the top level timing. | 02-11-2010 |
| 20110072407 | Automatic Positioning of Gate Array Circuits in an Integrated Circuit Design - An automated method and apparatus for positioning gate array circuits in an integrated circuit design. An initial integrated circuit design includes logic cells and gate array fill circuits positioned thereon. The gate array fill circuits are positioned in available space between the adjacent logic cells so as to fill the available space with the maximum gate array fill circuits. A gate array logic element to be positioned in the integrated circuit design, such as may be required by an engineering change to the circuit design, is automatically positioned between adjacent logic cells so as to allow for full utilization of any space remaining between the adjacent logic cells by gate array fill circuits. | 03-24-2011 |
| 20110113395 | Method, Electronic Design Automation Tool, Computer Program Product, and Data Processing Program for Creating a Layout for Design Representation of an Electronic Circuit and Corresponding Port for an Electronic Circuit - A method for creating a layout for design representation of an electronic circuit with at least one port. The method includes segmenting the at least one port in the design representation into different regions, classifying the different regions of the at least one port according to timing and/or electronic and/or layout characteristics, assigning a priority for each classified region of the at least one port according to rules based on the timing and/or electronic and/or layout characteristics, and routing the design representation by accessing at least one of the classified regions of the port according to an order of the assigned priorities. | 05-12-2011 |
| 20110113398 | Method and System for Providing Secondary Power Pins in Integrated Circuit Design - An integrated circuit (IC) design with multiple metal layers containing cells requiring secondary power supply. After placing the cells and stripes of a primary power/ground grid in metal layers of the IC design, specific cells are provided with secondary power stripes in a first metal layer. The secondary power stripes are designed in such a way that each secondary power/ground stripe exhibits a full overlap with a stripe of a corresponding primary power/ground grid in a different metal layer. Subsequently, signals from the IC design are routed, and power vias between the primary power/ground grid stripes and the secondary power/ground stripes are generated. | 05-12-2011 |
| 20110154283 | Shaping Ports in Integrated Circuit Design - A mechanism is provided for performing a detailed routing of a net joining ports in an integrated circuit. Extended port regions are created for the ports of the net of the integrated circuit, the extended port regions being shaped in such a way as to guarantee routing access to the ports. A wire corresponding to the net is then placed and the extended port regions of the ports are trimmed, thus identifying essential port regions required for connecting the wire to the ports and dispensable port regions not required for connecting the wire to the ports. The wiring resources are then updated by releasing the dispensable port regions so that the dispensable port regions no longer constitute parts of the ports. | 06-23-2011 |
