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| 20110212557 | METHOD OF MANUFACTURING AN ARRAY SUBSTRATE FOR LCD DEVICE HAVING DOUBLE-LAYERED METAL STRUCTURE - The present invention is an array substrate for use in a liquid crystal display device, which includes a gate electrode, a gate line and a gate pad on a substrate, wherein the gate electrode, the gate line and the gate pad have a double-layered structure consisting of a first metal layer and a first barrier metal layer in series from the substrate, and wherein the first metal is one of aluminum and aluminum alloy; a gate insulation layer on the substrate covering the gate electrode, gate line and gate pad; an active layer and an ohmic contact layer sequentially formed on the gate insulation layer and over the gate electrode; a data line on the gate insulation layer perpendicularly crossing the gate line, source and drain electrodes contacting the ohmic contact layer, and a data pad on the gate insulation layer, wherein the data line, the source and drain electrode and the data pad have a double-layered structure consisting of a second barrier metal layer and a second metal layer of copper; a passivation layer formed on the gate insulation layer to cover the data line, source and drain electrodes, and data pad, wherein the passivation layer has a drain contact hole exposing a portion of the drain electrode, a gate pad contact hole exposing a portion of the gate pad, and a data pad contact hole exposing a portion of the data pad; and a pixel electrode, a gate pad terminal and a data pad terminal on the passivation layer, all of which are formed of a transparent conductive material on the passivation layer. | 09-01-2011 |
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| 20110305064 | INTERFACE CONTROL FOR IMPROVED SWITCHING IN RRAM - A memory device has a crossbar array including a first array of first electrodes extending along a first direction. A second array of second electrodes extends along a second direction. A non-crystalline silicon structure provided between the first electrode and the second electrode at an intersection defined by the first array and the second array. The non-crystalline silicon structure has a first layer having a first defect density and a second layer having a second defect density different from the first defect density. Each intersection of the first array and the second array defines a two-terminal memory cell. | 12-15-2011 |
| 20110305065 | NON-VOLATILE VARIABLE CAPACITIVE DEVICE INCLUDING RESISTIVE MEMORY CELL - A non-volatile variable capacitive device includes a capacitor defined over a substrate, the capacitor having an upper electrode and a resistive memory cell having a first electrode, a second electrode, and a switching layer provided between the first and second electrodes. The resistive memory cell is configured to be placed in a plurality of resistive states according to an electrical signal received. The upper electrode of the capacitive device is coupled to the second electrode of the resistive memory cell. The resistive memory cell is a two-terminal device. | 12-15-2011 |
| 20110305066 | WRITE AND ERASE SCHEME FOR RESISTIVE MEMORY DEVICE - A method for programming a two terminal resistive memory device, the method includes applying a bias voltage to a first electrode of a resistive memory cell of the device; measuring a current flowing through the cell; and stopping the applying of the bias voltage if the measured current is equal to or greater than a predetermined value. | 12-15-2011 |
| 20110317470 | RECTIFICATION ELEMENT AND METHOD FOR RESISTIVE SWITCHING FOR NON VOLATILE MEMORY DEVICE - A method of suppressing propagation of leakage current in an array of switching devices. The method includes providing a dielectric breakdown element integrally and serially connected to a switching element within each of the switching device. A read voltage (for example) is applied to a selected cell. The propagation of leakage current is suppressed by each of the dielectric breakdown element in unselected cells in the array. The read voltage is sufficient to cause breakdown in the selected cells but insufficient to cause breakdown in the serially connected, unselected cells in a specific embodiment. Methods to fabricate of such devices and to program, to erase and to read the device are provided. | 12-29-2011 |
| 20120001146 | NANOSCALE METAL OXIDE RESISTIVE SWITCHING ELEMENT - A non-volatile memory device structure. The non-volatile memory device structure comprises a first electrode formed from a first metal material, a resistive switching element overlying the first electrode. The resistive switching element comprises a metal oxide material characterized by one or more oxygen deficient sites. The device includes a second electrode overlying the resistive switching layer, the second electrode being formed from a second metal material. The second electrode is made from a noble metal. The one or more oxygen deficient sites are caused to migrate from one of the first electrode or the second electrode towards the other electrode upon a voltage applied to the first electrode or the second electrode. The device can have a continuous change in resistance upon applying a continuous voltage ramp, suitable for an analog device. Alternatively, the device can have a sharp change in resistance upon applying the continuous voltage ramp, suitable for a digital device. | 01-05-2012 |
| 20120007035 | Intrinsic Programming Current Control for a RRAM - A resistive switching device. The device includes a substrate and a first dielectric material overlying a surface region of the substrate. The device includes a first electrode overlying the first dielectric material and an optional buffer layer overlying the first electrode. The device includes a second electrode structure. The second electrode includes at least a silver material. In a specific embodiment, a switching material overlies the optional buffer layer and disposed between the first electrode and the second electrode. The switching material comprises an amorphous silicon material in a specific embodiment. The amorphous silicon material is characterized by a plurality of defect sites and a defect density. The defect density is configured to intrinsically control programming current for the device. | 01-12-2012 |
| 20120015506 | TWO TERMINAL RESISTIVE SWITCHING DEVICE STRUCTURE AND METHOD OF FABRICATING - A method of forming a two terminal device. The method includes forming a first dielectric material overlying a surface region of a substrate. A bottom wiring material is formed overlying the first dielectric material and a switching material is deposited overlying the bottom wiring material. The bottom wiring material and the switching material is subjected to a first patterning and etching process to form a first structure having a top surface region and a side region. The first structure includes at least a bottom wiring structure and a switching element having a first side region, and a top surface region including an exposed region of the switching element. A second dielectric material is formed overlying at least the first structure including the exposed region of the switching element. The method forms an opening region in a portion of the second dielectric layer to expose a portion of the top surface region of the switching element. A top wiring material including a conductive material is formed overlying at lease the opening region such that the conductive material is in direct contact with the switching element. A second etching process is performed to form at least a top wiring structure. In a specific embodiment, the side region of the first structure including a first side region of the switching element is free from a contaminant conductive material from the second etching process. | 01-19-2012 |
| 20120043519 | DEVICE SWITCHING USING LAYERED DEVICE STRUCTURE - A resistive switching device. The device includes a first electrode comprising a first metal material overlying the first dielectric material and a switching material comprising an amorphous silicon material. The device includes a second electrode comprising at least a second metal material. In a specific embodiment, the device includes a buffer material disposed between the first electrode and the switching material. The buffer material provides a blocking region between the switching material and the first electrode so that the blocking region is substantially free from metal particles from the second metal material when a first voltage is applied to the second electrode. | 02-23-2012 |
| 20120074374 | CONDUCTIVE PATH IN SWITCHING MATERIAL IN A RESISTIVE RANDOM ACCESS MEMORY DEVICE AND CONTROL - A non-volatile memory device structure. The device structure includes a first electrode, a second electrode, a resistive switching material comprising an amorphous silicon material overlying the first electrode, and a thickness of dielectric material having a thickness ranging from 5 nm to 10 nm disposed between the second electrode and the resistive switching layer. The thickness of dielectric material is configured to electrically breakdown in a region upon application of an electroforming voltage to the second electrode. The electrical breakdown allows for a metal region having a dimension of less than about 10 nm by 10 nm to form in a portion of the resistive switching material. | 03-29-2012 |
| 20120074507 | INTEGRATION OF AN AMORPHOUS SILICON RESISTIVE SWITCHING DEVICE - An integrated circuit device. The integrated circuit device includes a semiconductor substrate having a surface region. A gate dielectric layer overlies the surface region of the substrate. The device includes a MOS device having a p+ active region. The p+ active region forms a first electrode for a resistive switching device. The resistive switching device includes an amorphous silicon switching material overlying the p+ active region and a metal electrode overlies the first metal conductor structure. The metal electrode includes a metal material, upon application of a positive bias to the metal electrode, forms a metal region in the amorphous silicon switching material. The MOS device provides for a select transistor for the integrated circuit device. | 03-29-2012 |
| 20120075907 | RESISTOR STRUCTURE FOR A NON-VOLATILE MEMORY DEVICE AND METHOD - A non-volatile resistive switching memory device. The device includes a first electrode, a second electrode, a switching material in direct contact with a metal region of the second electrode, and a resistive material disposed between the second electrode and the switching material. The resistive material has an ohmic characteristic and a resistance substantially the same as an on state resistance of the switching device. The resistive material allows for a change in a resistance of the switching material upon application of voltage pulse without time delay and free of a reverse bias after the voltage pulse. The first voltage pulse causes a programming current to flow from the second electrode to the first electrode. The resistive material further causes the programming current to be no greater than a predetermined value. | 03-29-2012 |
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| 20100188105 | CAPACITANCE-TO-VOLTAGE INTERFACE CIRCUIT, AND RELATED OPERATING METHODS - A capacitance-to-voltage interface circuit is utilized to obtain a voltage corresponding to a detected capacitance differential, which may be associated with the operation of a capacitive sensing cell. The interface circuit includes a capacitive sensing cell, an operational amplifier adapted for selective coupling to the capacitive sensing cell, a feedback capacitor for the operational amplifier, a load capacitor for the operational amplifier, and a switching architecture associated with the capacitive sensing cell, the operational amplifier, the feedback capacitor, and the load capacitor. During use, the switching architecture reconfigures the capacitance-to-voltage interface circuit for operation in a plurality of different phases. The different operational phases enable the single operational amplifier to be used for both capacitance-to-voltage conversion and voltage amplification. | 07-29-2010 |
| 20100188107 | CAPACITANCE-TO-VOLTAGE INTERFACE CIRCUIT WITH SHARED CAPACITOR BANK FOR OFFSETTING AND ANALOG-TO-DIGITAL CONVERSION - A capacitance-to-voltage interface circuit includes a capacitive sensing circuit, an amplification circuit adapted for selective coupling to the capacitive sensing circuit, a capacitor bank comprising a plurality of binary-weighted capacitors, and a switching architecture associated with the capacitive sensing circuit, the amplification circuit, and the capacitor bank. The switching architecture reconfigures the capacitance-to-voltage interface circuit for operation in a plurality of different phases, including an amplification phase and an analog-to-digital conversion phase. During the amplification phase, the capacitor bank is utilized for offsetting capacitance of the amplification circuit. During the analog-to-digital conversion phase, the capacitor bank is utilized in a successive approximation register. | 07-29-2010 |
| 20100188278 | CHARGE REDISTRIBUTION SUCCESSIVE APPROXIMATION ANALOG-TO-DIGITAL CONVERTER AND RELATED OPERATING METHOD - The analog-to-digital converter provided herein includes a capacitor bank comprising a plurality of binary-weighted capacitors, an operational amplifier having an inverting input node, a noninverting input node coupled to analog ground, and an output node, a reset switch, and an input switch. The reset switch is located between the capacitor bank and the operational amplifier, and it selectively couples the capacitor bank to the inverting input node. The input switch has its common terminal coupled to the capacitor bank, and the input switch selectively couples the capacitor bank to either an analog input voltage, a floating terminal, or analog ground. The capacitor bank includes N binary-weighted capacitors and one balacing capacitor that has a unit capacitance. During operation, the analog-to-digital converter generates an N-bit digital output and one polarity bit from the analog input voltage. | 07-29-2010 |
| 20110208460 | OFFSET ERROR AUTOMATIC CALIBRATION INTEGRATED CIRCUIT - An integrated circuit includes a transducer and transducer circuitry and additional elements useful in testing the transducer and transducer circuitry. A first power supply terminal and a second power supply terminal are for being directly connected to an external power supply terminal. A power bus is connected to the first power supply terminal. A logic function is for determining if the second power supply terminal is receiving power and if an automatic calibration test of the transducer and transducer circuitry has been run. An automatic calibration is for running an automatic calibration test on the transducer and transducer circuitry if the logic means determines that the second power supply terminal is receiving power and the automatic calibration test of the transducer and transducer circuitry has not been run. | 08-25-2011 |
| 20120105079 | CAPACITANCE-TO-VOLTAGE INTERFACE CIRCUITS - A capacitance-to-voltage interface circuit is utilized to obtain a voltage corresponding to a detected capacitance differential, which may be associated with the operation of a capacitive sensing cell. The interface circuit includes a capacitive sensing cell, an operational amplifier adapted for selective coupling to the capacitive sensing cell, a feedback capacitor for the operational amplifier, a load capacitor for the operational amplifier, and a switching architecture associated with the capacitive sensing cell, the operational amplifier, the feedback capacitor, and the load capacitor. During use, the switching architecture reconfigures the capacitance-to-voltage interface circuit for operation in a plurality of different phases. The different operational phases enable the single operational amplifier to be used for both capacitance-to-voltage conversion and voltage amplification. | 05-03-2012 |
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| 20120103101 | SYSTEMS, METHODS, AND APPARATUS FOR COMPENSATING ATMOSPHERIC PRESSURE MEASUREMENTS IN FIRED EQUIPMENT - Certain embodiments of the invention may include systems, methods, and apparatus for providing compensating atmospheric pressure measurements in fired equipment. According to an example embodiment of the invention, a method is provided compensating pressure measurements. The method includes providing a wind compensating ring tube having three or more apertures to equalize pressure inside the compensating ring tube, installing the wind compensating ring tube adjacent to a furnace, connecting a pressure transmission tube from the wind compensating ring tube to one or more pressure sensors, and transmitting pressure from inside the wind compensating ring tube to the one or more pressure sensors by the pressure transmission tube. | 05-03-2012 |
| 20120107752 | SYSTEMS, METHODS, AND APPARATUS FOR DETERMINING AIRFLOW THROUGH A BURNER - Certain embodiments of the invention may include systems, methods, and apparatus for determining airflow through a burner. According to an example embodiment of the invention, a method is provided for determining airflow through a burner. The method includes installing a first end of an inlet pressure transmission tube in an air inlet region of a furnace burner system, installing a first end of a burner pressure transmission tube in a burner exit region of the furnace burner system, connecting a second end of the inlet pressure transmission tube to a first pressure sensor, connecting a second end of the burner pressure transmission tube to a second pressure sensor, measuring the differential pressure between the first and second pressure sensors, and determining airflow based at least in part on the measured differential pressure. | 05-03-2012 |
