| Patent application number | Description | Published |
|---|
| 20080244512 | Code optimization based on loop structures - Instructions that have no dependence constraint between them and other instructions in a loop of a critical section may be moved out of the critical section so that the size of the critical section may be reduced. A flow graph of a program including the critical section may be generated, which includes loops. The flow graph may be transformed based on which any unnecessary instructions in loops may be moved out of the critical section. Subsequently, the original flow graph of the critical section may be recovered from the transformed flow graph. | 10-02-2008 |
| 20080282237 | Method and Apparatus For Generating Execution Equivalence Information - A method of compiling code includes identifying blocks of code that are execution equivalence pairs. Other embodiments are described and claimed. | 11-13-2008 |
| 20080288737 | Optimizing Memory Accesses for Network Applications Using Indexed Register Files - A processing device includes an optimizer to migrate objects from an external memory of a network processing to local memory device to registers connected to a processor. The optimizer further aligns and eliminates redundant unitialization code of the objects. | 11-20-2008 |
| 20090037889 | SPECULATIVE CODE MOTION FOR MEMORY LATENCY HIDING - Various embodiments that may be used in performing speculative code motion for memory latency hiding are disclosed. One embodiment comprises extracting an asynchronous signal from a memory access instruction in a program to represent a latency of the memory access instruction, and generating a wait instruction to wait the asynchronous signal. | 02-05-2009 |
| 20090043991 | Scheduling Multithreaded Programming Instructions Based on Dependency Graph - A computer implemented method for scheduling multithreaded programming instructions based on the dependency graph wherein the dependency graph organizes the programming instruction logically based on blocks, nodes, and super blocks and wherein the programming instructions could be executed outside of a critical section may be executed outside of the critical section by inserting dependency relationship in the dependency graph. | 02-12-2009 |
| 20090049433 | Method and apparatus for ordering code based on critical sections - A method of compiling code includes ordering instructions that protect and release critical sections in the code to improve parallel execution of the code according to an intrinsic order of the critical sections. According to one embodiment, the intrinsic order of the critical sections in the code is determined from data dependence and control dependence of instructions in the critical sections, and additional dependencies are generated to enforce the intrinsic order of the critical sections. Other embodiments are described and claimed. | 02-19-2009 |
| 20090089765 | CRITICAL SECTION ORDERING FOR MULTIPLE TRACE APPLICATIONS - Critical sections in a programming code may be ordered based at least in part on code motions. A flow graph of the code including the critical section may be generated. Two initiative motions may be performed based on the flow graph to identify possible positions of critical codes in the flow graph. Dependence relationship of critical sections may be determined based on the positions of critical sections. Using the dependence relationship information, the order of critical sections may be determined. The determined order of critical sections may be further used by a compiler to perform optimizations for the code. | 04-02-2009 |
| 20090193405 | Method and apparatus for partitioning programs to balance memory latency - A method of compiling code that includes partitioning instructions in the code among a plurality of processors based on memory access latency associated with the instructions is disclosed. According to one aspect of the invention, partitioning instructions includes partitioning memory access dependence chains. Other embodiments are described and claimed. | 07-30-2009 |
| 20100223605 | APPARATUS AND METHOD FOR AUTOMATICALLY PARALLELIZING NETWORK APPLICATIONS THROUGH PIPELINING TRANSFORMATION - In some embodiments, a method and apparatus for automatically parallelizing a sequential network application through pipeline transformation are described. In one embodiment, the method includes the configuration of a network processor into a D-stage processor pipeline. Once configured, a sequential network application program is transformed into D-pipeline stages. Once transformed, the D-pipeline stages are executed in parallel within the D-stage processor pipeline. In one embodiment, transformation of a sequential application program is performed by modeling the sequential network program as a flow network model and selecting from the flow network model into a plurality of preliminary pipeline stages. Other embodiments are described and claimed. | 09-02-2010 |
