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Jinghong
Jinghong Chen, Basking Ridge, NJ US
| Patent application number | Description | Published |
|---|---|---|
| 20090085642 | PASSIVE MIXER HAVING TRANSCONDUCTANCE AMPLIFIER WITH SOURCE DEGENERATION CAPACITANCE - A passive mixer includes a transconductance amplifier having a source degeneration capacitance. The transconductance amplifier has an input for receiving an input signal and an output for outputting a current signal. A multiplier is provided for mixing a local oscillator signal with the current signal so as to provide an output signal at an output of the passive mixer. A capacitive load is connected to the output of the passive mixer. | 04-02-2009 |
| 20090212856 | ANALOG AMPLIFIER HAVING DC OFFSET CANCELLATION CIRCUIT AND METHOD OF OFFSET CANCELLATION FOR ANALOG AMPLIFIERS - An amplifier having DC offset compensation includes at least one input node and a pair of differential output nodes, a biasing circuit coupled to the input node; and a plurality of current sources. Selected ones of said current sources are coupled to the input node to adjust a DC voltage at the input node to provide DC offset compensation for the amplifier | 08-27-2009 |
Jinghong Guo, Torrance, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20090121695 | METHODS AND APPARATUS FOR A MULTIPHASE POWER REGULATOR - Methods and apparatus for a multiphase power regulator according various aspects of the present invention operate in conjunction with an active transient response (ATR) system for applying a correction signal to a multiphase pulse width modulator. In the event of a transient, the ATR system may adjust the output of the pulse width modulator to quickly respond to load requirements. The output may be modified by adding pulses, blanking pulses, advancing pulses, and scaling pulses to one or more phases. | 05-14-2009 |
| 20090146620 | METHODS AND APPARATUS FOR CURRENT SENSING - Methods and apparatus for current sensing according to various aspects of the present invention operate in conjunction with a current sensor adapted to sense the current provided to a load via a transistor. In one embodiment, a power supply includes the current sensor, and supplies the current through a series combination of an inductor and the transistor. The current sensor is adapted to generate the inductor current signal according to a sensed current in the inductor, and may comprise a series combination of a first resistor and a second resistor. The resistive series combination is adapted to be connected in parallel to the series combination of the inductor and the transistor. | 06-11-2009 |
Jinghong Li, Hopewell Junction, NY US
| Patent application number | Description | Published |
|---|---|---|
| 20110062518 | finFETS AND METHODS OF MAKING SAME - A method of fabricating and a structure of a merged multi-fin finFET. The method includes forming single-crystal silicon fins from the silicon layer of an SOI substrate having a very thin buried oxide layer and merging the end regions of the fins by growing vertical epitaxial silicon from the substrate and horizontal epitaxial silicon from ends of the fins such that vertical epitaxial silicon growth predominates. | 03-17-2011 |
| 20110095343 | BI-LAYER nFET EMBEDDED STRESSOR ELEMENT AND INTEGRATION TO ENHANCE DRIVE CURRENT - A semiconductor structure including a bi-layer nFET embedded stressor element is disclosed. The bi-layer nFET embedded stressor element can be integrated into any CMOS process flow. The bi-layer nFET embedded stressor element includes an implant damaged free first layer of a first epitaxy semiconductor material having a lattice constant that is different from a lattice constant of a semiconductor substrate and imparts a tensile strain in a device channel of an nFET gate stack. Typically, and when the semiconductor is composed of silicon, the first layer of the bi-layer nFET embedded stressor element is composed of Si:C. The bi-layer nFET embedded stressor element further includes a second layer of a second epitaxy semiconductor material that has a lower resistance to dopant diffusion than the first epitaxy semiconductor material. Typically, and when the semiconductor is composed of silicon, the second layer of the bi-layer nFET embedded stressor element is composed of silicon. Only the second layer of the bi-layer nFET embedded stressor element includes the implanted source/drain regions. | 04-28-2011 |
Jinghong Li, Poughquag, NY US
| Patent application number | Description | Published |
|---|---|---|
| 20080246056 | SILICIDE FORMATION FOR eSiGe USING SPACER OVERLAPPING eSiGe AND SILICON CHANNEL INTERFACE AND RELATED PFET - Methods of forming a suicide in an embedded silicon germanium (eSiGe) source/drain region using a suicide prevention spacer overlapping an interface between the eSiGe and the silicon channel, and a related PFET with an eSiGe source/drain region and a compressive stress liner in close proximity to a silicon channel thereof, are disclosed. In one embodiment, a method includes providing a gate having a nitrogen-containing spacer adjacent thereto and an epitaxially grown silicon germanium (eSiGe) region adjacent to a silicon channel of the gate; removing the nitrogen-containing spacer that does not extend over the interface between the eSiGe source/drain region and the silicon channel; forming a single silicide prevention spacer about the gate, the single silicide prevention spacer overlapping the interface; and forming the silicide in the eSiGe source/drain region using the single silicide prevention spacer to prevent the silicide from forming in at least an extension area of the silicon channel. | 10-09-2008 |
| 20100200896 | EMBEDDED STRESS ELEMENTS ON SURFACE THIN DIRECT SILICON BOND SUBSTRATES - A method for growing an epitaxial layer on a substrate wherein the substrate includes a surface having a Miller index of (110) for the beneficial properties. The method comprises using a direct silicon bonded wafer with a substrate having a first Miller index and a surface having a second Miller index. An element such as a gate for a PFET may be deposited onto the surface. The area not under the gate may then be etched away to expose the substrate. An epitaxial layer may then be grown on the surface providing optimal growth patterns. The Miller index of the substrate may be (100). In an alternative embodiment the surface may have a Miller index of (100) and the surface is etched where an element such as a gate for a PFET may be placed. | 08-12-2010 |
Jinghong Li, San Jose, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20090099669 | MONITORING AND CONTROL OF ELECTRONIC DEVICES - A method, a system, and a computer program product for managing one or more electronic devices. Performance of an electronic device is monitored and presented to a user through a digital agent interface. The performance of the electronic device is controlled automatically by digital agent through the digital agent interface. The invention also enables automatic testing of the electronic device through the digital agent interface by setting up test configurations, activating test signals, and interpreting any error codes that may be generated. | 04-16-2009 |