| Patent application number | Description | Published |
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| 20100022067 | DEPOSITION METHODS FOR RELEASING STRESS BUILDUP - A deposition method for releasing a stress buildup of a feature over a semiconductor substrate with dielectric material is provided. The feature includes lines separated by a gap. The method includes forming a liner layer over the feature on the semiconductor substrate in a chamber. A stress of the liner layer over the feature is released to substantially reduce bending of the lines of the feature. A dielectric film is deposited over the stress-released liner layer to substantially fill the gap of the feature. | 01-28-2010 |
| 20100062603 | SEMICONDUCTOR DEVICES SUITABLE FOR NARROW PITCH APPLICATIONS AND METHODS OF FABRICATION THEREOF - Semiconductor devices suitable for narrow pitch applications and methods of fabrication thereof are described herein. In some embodiments, a semiconductor device may include a floating gate having a first width proximate a base of the floating gate that is greater than a second width proximate a top of the floating gate. In some embodiments, a method of shaping a material layer may include (a) oxidizing a surface of a material layer to form an oxide layer at an initial rate; (b) terminating formation of the oxide layer when the oxidation rate is about 90% or below of the initial rate; (c) removing at least some of the oxide layer by an etching process; and (d) repeating (a) through (c) until the material layer is formed to a desired shape. In some embodiments, the material layer may be a floating gate of a semiconductor device. | 03-11-2010 |
| 20110053380 | SILICON-SELECTIVE DRY ETCH FOR CARBON-CONTAINING FILMS - A method of etching silicon-and-carbon-containing material is described and includes a SiConi™ etch in combination with a flow of reactive oxygen. The reactive oxygen may be introduced before the SiConi™ etch reducing the carbon content in the near surface region and allowing the SiConi™ etch to proceed more rapidly. Alternatively, reactive oxygen may be introduced during the SiConi™ etch further improving the effective etch rate. | 03-03-2011 |
| 20110151674 | SMOOTH SICONI ETCH FOR SILICON-CONTAINING FILMS - A method of etching silicon-containing material is described and includes a SiConi™ etch having a greater or lesser flow ratio of hydrogen compared to fluorine than that found in the prior art. Modifying the flow rate ratios in this way has been found to reduce roughness of the post-etch surface and to reduce the difference in etch-rate between densely and sparsely patterned areas. Alternative means of reducing post-etch surface roughness include pulsing the flows of the precursors and/or the plasma power, maintaining a relatively high substrate temperature and performing the SiConi™ in multiple steps. Each of these approaches, either alone or in combination, serve to reduce the roughness of the etched surface by limiting solid residue grain size. | 06-23-2011 |
| 20110151676 | METHODS OF THIN FILM PROCESS - A method for forming a semiconductor structure includes forming a plurality of features across a surface of a substrate, with at least one space being between two adjacent features. A first dielectric layer is formed on the features and within the at least one space. A portion of the first dielectric layer interacts with a reactant derived from a first precursor and a second precursor to form a first solid product. The first solid product is decomposed to substantially remove the portion of the first dielectric layer. A second dielectric layer is formed to substantially fill the at least one space. | 06-23-2011 |
| 20110230052 | INVERTABLE PATTERN LOADING WITH DRY ETCH - A method of etching silicon oxide from a narrow trench and a wide trench (or open area) is described which allows the etch in the wide trench to progress further than the etch in the narrow trench. The method includes two dry etch cycles. The first dry etch cycle involves a low intensity or abbreviated sublimation step which leaves solid residue in the narrow trench. The remaining solid residue inhibits etch progress in the narrow trench during the second dry etch cycle allowing the etch in the wide trench to overtake the etch in the narrow trench. | 09-22-2011 |
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| 20090245718 | Optical Sensor And Method Employing Half-Core Hollow Optical Waveguide - An optical sensor, sensing system and method of sensing employ a half-core hollow optical waveguide adjacent to a surface of an optical waveguide layer of a substrate. The half-core hollow optical waveguide and the adjacent optical waveguide layer cooperatively provide both an optical path that confines and guides an optical signal and an internal hollow channel. The optical path and channel extend longitudinally along a hollow core of the half-core hollow optical waveguide. The system further includes an optical source at an input of the optical path and an optical detector at an output of the optical path. A spectroscopic interaction between an analyte material that is introduced into the channel and an optical signal propagating along the optical path determines a characteristic of the analyte material. | 10-01-2009 |
| 20100079754 | SYSTEMS FOR PERFORMING RAMAN SPECTROSCOPY - Various embodiments of the present invention relate generally to systems for performing Raman spectroscopy. In one embodiment, a system for performing Raman spectroscopy comprises an analyte holder having a surface configured to retain an analyte and a light concentrator configured to receive an incident beam of light, split the incident beam into one or more beams, and direct the one or more beams to substantially intersect at the surface. The system may also include a collector configured to focus each of the one or more beams onto the surface, collect the Raman scattered light emitted from the analyte, and direct the Raman scattered light away from the surface. | 04-01-2010 |
| 20110227032 | Memristor with Nanostructure Electrodes - A memristor having an active region includes a first electrode. The first electrode comprises a nanostructure formed of at least one metallic single walled nanotube. The memristor also includes a second electrode formed of at least one metallic single walled nanotube. The second electrode is positioned in a crossed relationship with respect to the first electrode. The memristor further includes a switching material positioned between the first electrode and the second electrode, in which the active region is configured to form in the switching material at a cross point of the first electrode and the second electrode. | 09-22-2011 |
| 20110228266 | SUBSTRATE FOR SURFACE ENHANCED RAMAN SCATTERING (SERS) - A substrate for Surface Enhanced Raman Scattering (SERS). The substrate comprises at least one nanostructure protruding from a surface of the substrate and a SERS active metal over the at least one nanostructure, wherein the SERS active metal substantially covers the at least one nanostructure and the SERS active metal creates a textured layer on the at least one nanostructure. | 09-22-2011 |
